PCM Signal processor

Claim 2

A pulse code modulation (PCM) signal processor for extracting data words from a serial PCM data block also containing an error detection and correction code, said signal processor comprising: serial-to-parallel converter means for converting said serial PCM data block into a parallel format, said serial-to-parallel converting means having terminals each outputting in parallel a different one of said data words and said error detection and correction code; de-interleave means conneected to said terminals of said serial-to-parallel converter means for adding different delays to said data words such that all of said data words appear synchronously at the output of said de-interleave means; means connected to said terminals of said serial-to-parallel converter means for forming an error pointer from said data words and said error detection and correction code, said error pointer comprising data word error pointers each indicating the presence of an error in a different one of said data words; an error pointer shift register connected to said error pointer forming means for synchronizing said error pointer with said de-interleave means such that each data word error pointer is synchronized with its corresponding data word; and means connected to said error pointer shift register and to said de-interleave means for detecting and correcting errors in said data words from said de-interleave means using said data word error pointers from said error pointer shift register.

Claim 3

A pulse code modulation (PCM) signal processor for extracting data words from a serial PCM data block also containing an error detection and correction code, said signal processor comprising: serial-to-parallel converter means for converting said serial PCM data block into a parallel format, said serial-to-parallel converting means having terminals each outputting in parallel a different one of said data words and said error detection and correction code; de-interleave means connected to said terminals of said serial-to-parallel converter means for adding different delays to said data words such that all of said data words appear synchronously at the output of said de-interleave means, said de-interleave means containing means to impart no delay to a last data word occurring later than the other data words in said serial PCM data block and adding a delay iD to the data words other than said last data word, where D is a time required to transmit one data word in said PCM data block and where i is an integer indicating the number of data word positions of a particular data word from said last data word; means connected to said terminals of said serial-to-parallel converter means for forming an error pointer from said data words and said error detection and correction code, said error pointer comprising data word error pointers each indicating the presence of an error in a different one of said data words; an error pointer shift register connected to said error pointer forming means for synchronizing said error pointer with said de-interleave means such that each data word error pointer is synchronized with its corresponding data word, said error pointer shift register including means to shift said error pointer at a rate equal to 1/D; and means connected to said error pointer shift register to said de-interleave means for detecting and correcting errors in said data words from said de-interleave means using said data word error pointers from said error pointer shift register.

Claim 4

A pulse code modulation (PCM) signal processor for extracting data words from a serial PCM data block also containing an error detection and correction code, said signal processor comprising: serial-to-parallel converter means for converting said serial PCM data block into a parallel format, said serial-to-parallel converting means having terminals each outputting in parallel a different one of said data words and said error detection and correction code; de-interleave means connected to said terminals of said serial-to-parallel converter means for adding different delays to said data words such that all of said data words appear synchronously at the output of said de-interleave means, said de-interleave means containing means to impart no delay to a last data word occurring later than the other data words in said serial PCM data block and adding a delay iD to the data words other than said last data word, where D is a time required to transmit one data word in said PCM data block and where i is an integer indicating the number of data word positions of a particular data word from said last data word; means connected to said terminals of said serial-to-parallel converter means for forming an error pointer from said data words and said error detection and correction code, said error pointer comprising data word error pointers each indicating the presence of an error in a different one of said data words; an error pointer shift register connected to said error pointer forming means for synchronizing said error pointer with said de-interleave means such that each data word error pointer is synchronized with its corresponding data word, said error pointer shift register including means to shift said error pointer at a rate equal to 1/D; and means connected to said error pointer shift register to said de-interleave means for detecting and correcting errors in said data words from said de-interleave means using said data word error pointers from said error pointer shift register.

Claim 5

The PCM signal processor in claim 2 wherein said error pointer shift register comprises a serial shift register including a number of independent stages, said number of stages being equal to one less than the number of data words in sad PCM data block, each of said stages having a separate output and imparting the same preset delay to the signal at its input.

Claim 6

The PCM signal processor in claim 2 wherein said error pointer shift register includes a number of storage registers, said number of registers being one less than the number of data words in said PCM data block, each of said registers having an input and an output, the output of a register being connected to the input of a succeeding register and each of said registers imparting the same preset delay to the signal at its input.

Claim 7

A pulse code modulation (PCM) signal processor for extracting data words from a serial PCM data block also containing an error detection and correction code, said signal processor comprising: serial-to-parallel converter means for converting said serial PCM data block into a parallel format, said serial-to-parallel converting means having terminals each outputting in parallel a different one of said data words in said error detection and correction code; de-interleave means connected to said terminals of said serial-to-parallel converter means for adding different delays to said data words such that all of said data words appear synchronously at the output of de-interleave means; means connected to said terminals of said serial-to-parallel converter means for forming an error pointer from said data words and said error detection and correction code, said error pointer comprising data word error pointers each indicating the presence of an error in a different one of said data words; an error pointer shift register connected to said error pointer forming means for synchronizing said error pointer with said de-interleave means such that each data word error pointer is synchronized with its corresponding data word, said error pointer shift register including a serial shift register having a number of indpendent stages, said number of stages being equal to one less than the number of data words in said PCM data block and each of said stages having a separate output and imparting the same preset delay to the signal at its input; and means connected to said error pointer shift register and to said de-interleave means for detecting and correcting errors in said data words from said de-interleave means using said data word error pointers from said error pointer shift register.

Claim 8

A pulse code modulation (PCM) signal processor for extracting data words from a serial PCM data block also containing an error detection and correction code, said signal processor comprising: serial-to-parallel converter means for converting said serial PCM data block into a parallel format, said serial-to-parallel converting means having terminals each outputting in parallel a different one of said data words in said error detection and correction code; de-interleave means connected to said terminals of said serial-to-parallel converter means for adding different delays to said data words such that all of said data words appear synchronously at the output of de-interleave means; means connected to said terminals of said serial-to-parallel converter means for forming an error pointer from said data words and said error detection and correction code, said error pointer comprising data word error pointers each indicating the presence of an error in a different one of said data words; an error pointer shift register connected to said error pointer forming means for synchronizing said error pointer with said de-interleave means such that each data word error pointer is synchronized with its corresponding data word, said error pointer shift register including a serial shift register having a number of indpendent stages, said number of stages being equal to one less than the number of data words in said PCM data block and each of said stages having a separate output and imparting the same preset delay to the signal at its input; and means connected to said error pointer shift register and to said de-interleave means for detecting and correcting errors in said data words from said de-interleave means using said data word error pointers from said error pointer shift register.

Claim 9

A pulse code modulation (PCM) signal processor for extracting data words from a serial PCM data block also containing an error detection and correction code, said signal processor comprising: serial-to-parallel converter means for converting said serial PCM data block into a parallel format, said serial-to-parallel converting means having terminals each outputting in parallel a different one of said data words and said error detection and correction code; de-interleave means connected to said terminals of said serial-to-parallel converter means for adding different delays to said data words such that all of said data words appear synchronously at the output of said de-interleave means; means connected to said terminals of said serial-to-parallel converter means for forming an error pointer from said data words and said error detection and correction code, said error pointer comprising data word error pointers each indicating a presence of an error in a different one of said data words; an error pointer shift register connected to said error pointer forming means for synchronizing said error pointer with said de-interleave means such that each data word error pointer is synchronized with its corresponding data word, said error pointer shift register including a number of storage registers, said number of registers being one less than the number of data words in said PCM data block and each of said registers having an input and an output, the output of a register being connected to the input of a succeeding register and each of said registers imparting the same preset delay to the signal at its input; and means connected to said error pointer shift register and to said de-interleave means for detecting and correcting errors in said data words from said de-interleave means using said data word error pointers from said error pointer shift register.

Claim 10

A pulse code modulation (PCM) signal processor for extracting data words from a serial PCM data block also containing an error detection and correction code, said signal processor comprising: serial-to-parallel converter means for converting said serial PCM data block into a parallel format, said serial-to-parallel converting means having terminals each outputting in parallel a different one of said data words and said error detection and correction code; de-interleave means connected to said terminals of said serial-to-parallel converter means for adding different delays to said data words such that all of said data words appear synchronously at the output of said de-interleave means; means connected to said terminals of said serial-to-parallel converter means for forming an error pointer from said data words and said error detection and correction code, said error pointer comprising data word error pointers each indicating a presence of an error in a different one of said data words; an error pointer shift register connected to said error pointer forming means for synchronizing said error pointer with said de-interleave means such that each data word error pointer is synchronized with its corresponding data word, said error pointer shift register including a number of storage registers, said number of registers being one less than the number of data words in said PCM data block and each of said registers having an input and an output, the output of a register being connected to the input of a succeeding register and each of said registers imparting the same preset delay to the signal at its input; and means connected to said error pointer shift register and to said de-interleave means for detecting and correcting errors in said data words from said de-interleave means using said data word error pointers from said error pointer shift register.