Block signal forming digital processor with error correction

Claim 1

A digital signal processing apparatus for use in recording a composite digital signal composed of modulated digital signals, obtained by digitally processing an information signal with a specific sampling period and composite synchronizing signals, and reproducing the same to restore an original information signal, said digital signal processing apparatus comprising: time-multiplexing means provided with an input signal; a first correction signal generation circuit supplied with the output of said time-multiplexing means, in which, by considering a digital signal of one sampling period as an element, and from a group $ comprising a plurality of said elements, each of m (m is a given integer) elements undergo a modulo-2 addition, forming a first correction signal p by use of said elements of said group $ without duplication, for producing a group P of said first correction signal p by similarly using all the elements in said group $ only once; a first delay device group supplied with the output of said time-multiplexing means, for selecting n (n is a given integer) elements at a time from said group $ without duplication with less than or equal to one element in common with said generation element of said correction signal p; a second correction signal generation circuit supplied with the output of said first delay device group, for forming a second correction signal q by the modulo-2 addition of said selected elements from said first delay device group, and also similarly producing a group Q comprising said second correction signal q by using all the elements in said group $ only once; a second delay device group supplied with the outputs of said first and second correction signal generation circuits, for producing L/m (L is a multiple of m and n) first correction signal p and L/n second correction signal q of said groups P and Q, respectively, in response to the outputs of said first and second correction signal generation circuits; a third delay device group supplied with the output of said first delay device group, for selecting L elements of said group $ excluding said elements forming said first and second correction signals from the output of said first delay device group; a block signal forming device supplied with the outputs of said second and third delay device groups, for generating an output block signal which is recorded onto a recording medium in the form of a digital signal; and a restoration circuit supplied with the first and second correction signals together with the generation elements thereof, both of which are reproduced from the recording medium, to restore the generation elements; said block signal forming device forming the block signal from the outputs of said second and third delay device groups and an error checking signal, in such a manner that the delayed first and second correction signals p and q and their generation elements form mutually different block signals.