Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
159 words
An error correction system for data bytes D to be arranged serially on a recording medium, comprising: encoder means for generating two check bytes C1 and C2 from k data bytes spaced n data bytes apart from each other in the serial sequence wherein the first check byte C1 D1 + D2 + D3 . . . + Dk and second check byte C2 T D1 + T2 D2 + T3 D3 . . . + Tk Dk where T is the companion matrix of a binary primative polynomial g(x) of degree f and lambda is any integer given by the expression t(2f-1)/(2b-1) in which t is any positive integer prime to 2b-1; means for adding these 2n check bytes at the end of the string of k X n data bytes they are produced from and, synchronization pulse means providing a periodic synchronization burst of non data pulses in series with the data byte to synchronize the data.
Claim 2
Dependent Claim
159 words
An error correction system for data bytes D to be arranged serially on a recording medium, comprising: encoder means for generating two check bytes C1 and C2 from k data bytes spaced n data bytes apart from each other in the serial sequence wherein the first check byte C1 D1 + D2 + D3 . . . + Dk and second check byte C2 T D1 + T2 D2 + T3 D3 . . . + Tk Dk where T is the companion matrix of a binary primative polynomial g(x) of degree f and lambda is any integer given by the expression t(2f-1)/(2b-1) in which t is any positive integer prime to 2b-1; means for adding these 2n check bytes at the end of the string of k X n data bytes they are produced from and, synchronization pulse means providing a periodic synchronization burst of non data pulses in series with the data byte to synchronize the data.
Claim 3
Dependent Claim
24 words
The error correction system of claim 1 including encoding means for Encoding each data digit in said data bytes in bit pairs or couples.
Claim 4
Dependent Claim
25 words
The error correction system of claim 2 wherein said synchronization pulse means is a means for generating an invalid code sequence of said bit pairs.
Claim 5
Dependent Claim
33 words
The error correction system of claim 1 wherein said encoding means is a means for providing encoded sequennce of data bit pairs that meet charge constraints and maximum and minimum run length constraints.
Claim 6
Dependent Claim
38 words
The error correction system of claim 4 wherein said synchronization pulse means is a means for generating a code sequence that violates said charge constraints but not the minimum or maximum run length constraints of said encoding means.
Claim 7
Dependent Claim
47 words
The error correction system of claim 1 wherein said synchronizing pulses means includes means for providing a burst of non data pulses after each n data bytes used to calculate different check digits C1 and C2 and after n check bytes C1 and n check bytes C2.
Claim 8
Dependent Claim
25 words
The error correction system of claim 6 wherein said encoder means is for encoding said data and check digits in a zero modulation (ZM) code.
Claim 9
Dependent Claim
29 words
The error correction system of claim 7 wherein said synchronization pulse means includes means for generating an invalid ZM waveform pattern including the bits 00101000101000 or the bits 00010100010100.
Claim 10
Dependent Claim
20 words
The correction system of claim 6 including pointer means for detecting errors in said ZM coded data and check digits.