US4433412A
Expired / Lapsed
US
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Method and apparatus for testing and verifying the operability of register based state machine apparatus
Assignee: Boeing North American Inc
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Filing: 1981-05-15
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Granted: 1984-02-21
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Expires: 2001-05-15
Abstract
Abstract When a state machine such as a computer is inoperative, the flow of data can occur in so many different ways that it is at times difficult to ascertain the portions of the state machine that are causing the problems. Whether the problems are caused by original design or later failure of components, the present invention can determine at least the general area of the problem and often the specific bit introducing the problem, by setting a predefined control bit pattern into a register and ascertaining whether or not the bit pattern returned to the register after a predefined sequence of operations matches design expectations. As illustrated, this may take the form of serially inserting data into a normally parallel operated register to form the predefined control bit pattern, which then is applied to a sequencer whose output address is used to address a word in ROM, and the addressed word as well as the address itself, is loaded into the register. The address and addressed word are then compared with design expectations to determine whether or not there is a problem with that particular instruction or that particular location in ROM.
Inventors
- 👤 David W. Best
- 👤 Jeffrey D. Russell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763; G06F11/22
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
176 words
State machine test apparatus comprising, in combination: instruction register means including an address section and a data path section; read only memory (ROM) means, connected to said register means for supplying addressed words thereto in response to receipt of appropriate input address signals; sequencer means connected between said register means and said ROM means for supplying said input address signals to both said ROM means and to said address section of said register means in response to receipt of appropriate control signals from said register means; test signal supply means, connected to said register means, for supplying predetermined instructions to said register means whereby addressed words are returned to said register means from said ROM means; and test signal apparatus output means for outputting from said register means both the addressed word returned by said ROM means in response to a predetermined instruction as supplied by said test signal supply means and the address last stored in said register means from said sequencer means, whereby the outputted word can be compared to a predetermined desired response.
Claim 2
Dependent Claim
176 words
State machine test apparatus comprising, in combination: instruction register means including an address section and a data path section; read only memory (ROM) means, connected to said register means for supplying addressed words thereto in response to receipt of appropriate input address signals; sequencer means connected between said register means and said ROM means for supplying said input address signals to both said ROM means and to said address section of said register means in response to receipt of appropriate control signals from said register means; test signal supply means, connected to said register means, for supplying predetermined instructions to said register means whereby addressed words are returned to said register means from said ROM means; and test signal apparatus output means for outputting from said register means both the addressed word returned by said ROM means in response to a predetermined instruction as supplied by said test signal supply means and the address last stored in said register means from said sequencer means, whereby the outputted word can be compared to a predetermined desired response.
Claim 3
Dependent Claim
170 words
Apparatus for testing a section of a microprocessor including a read only memory comprising, in combination: register means including serial control input means, parallel addressed word input means, parallel control bit pattern output means, and serial verification output means; means for initially setting the logic states of said register means to a predefined control bit pattern by serially entering said pattern by said serial control input means; read only memory (ROM) means, including instruction sequencing means, connected between said control bit pattern output means of said register means and said addressed word input means of said register means in a feedback manner for loading the next instruction in an instruction set into said register means from said read only means upon occurrence of a clock signal; means for operating the microprocessor for a predetermined number of clock cycles; and means for comparing the logic bits of the received addressed word serially removed from said register by said serial verification output means with a predetermined standard for the control bit pattern.
Claim 4
Dependent Claim
170 words
Apparatus for testing a section of a microprocessor including a read only memory comprising, in combination: register means including serial control input means, parallel addressed word input means, parallel control bit pattern output means, and serial verification output means; means for initially setting the logic states of said register means to a predefined control bit pattern by serially entering said pattern by said serial control input means; read only memory (ROM) means, including instruction sequencing means, connected between said control bit pattern output means of said register means and said addressed word input means of said register means in a feedback manner for loading the next instruction in an instruction set into said register means from said read only means upon occurrence of a clock signal; means for operating the microprocessor for a predetermined number of clock cycles; and means for comparing the logic bits of the received addressed word serially removed from said register by said serial verification output means with a predetermined standard for the control bit pattern.
Claim 5
Dependent Claim
31 words
Apparatus as claimed in claim 2 comprising in addition means for comparing the address supplied to said ROM means in each test with a predetermined address for each control bit pattern.
Claim 6
Dependent Claim
172 words
Apparatus for testing a memory programmed control state machine comprising, in combination: register means including serial and parallel input means, clock means and serial and parallel output means, said register means normally operating with parallel inputs and parallel outputs and upon command operating with either serial inputs or serial outputs; means connected to said clock means to supply clock signals to said register means; read only memory means, including sequencing means, connected between said parallel output means of said register means and said parallel input means of said register means and connected to said clock means for providing a feedback next instruction of an instruction set to said register means from said read only memory means in accordance with received clock signals; means connected to said serial input means of said register means for serially shifting an instruction into said register means; means for operating the control state machine for a predetermined number of clock cycles; and means for serially shifting the addressed word from said serial output means of register means.
Claim 7
Dependent Claim
172 words
Apparatus for testing a memory programmed control state machine comprising, in combination: register means including serial and parallel input means, clock means and serial and parallel output means, said register means normally operating with parallel inputs and parallel outputs and upon command operating with either serial inputs or serial outputs; means connected to said clock means to supply clock signals to said register means; read only memory means, including sequencing means, connected between said parallel output means of said register means and said parallel input means of said register means and connected to said clock means for providing a feedback next instruction of an instruction set to said register means from said read only memory means in accordance with received clock signals; means connected to said serial input means of said register means for serially shifting an instruction into said register means; means for operating the control state machine for a predetermined number of clock cycles; and means for serially shifting the addressed word from said serial output means of register means.
Claim 8
Dependent Claim
22 words
Apparatus as claimed in claim 4 wherein the signal serially shifted from said register means is compared with a predetermined result word.
Claim 9
Dependent Claim
41 words
Apparatus as claimed in claim 4 comprising in addition: means connected to said register means for storing therein the address supplied to said memory means; and means for serially shifting said address from said register means along with said addressed word.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-20 | 1987-08-22 | 1988-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-20 | 1991-08-22 | 1992-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-20 | 1995-08-22 | 1996-02-21 | $7700.00 | Window Closed / Lapsed |