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US4433393A
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US
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-10-13
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Granted: 1984-02-21
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Expires: 2001-10-13
Abstract
Abstract A static type semiconductor RAM device having a plurality of memory cells disposed at the cross points between word lines and bit lines, load circuits each connected between one of the bit lines and a voltage source, and, a charging circuit which electrically charges all the bit lines during the short time when all the word lines are in a non-selected condition.
Inventors
- 👤 Atsushi Oritani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:51
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
139 words
An improved semiconductor memory device of the type including a plurality of word lines, a plurality of bit lines crossing said word lines, a plurality of memory cells disposed at the cross points between said word lines and said bit lines, and load circuits each connected between one of said bit lines and a voltage source, a memory cell disposed at the cross point of a word line and a bit line being selected by selecting said word line and said bit line, wherein the improved memory device further comprises charging circuit means, operatively connected in parallel with said load circuits, for detecting the switching period when the potentials of all the word lines are at the potential level of a non-selected condition and for electrically charging all the bit lines during the switching period of word line potentials.
Claim 2
Dependent Claim
139 words
An improved semiconductor memory device of the type including a plurality of word lines, a plurality of bit lines crossing said word lines, a plurality of memory cells disposed at the cross points between said word lines and said bit lines, and load circuits each connected between one of said bit lines and a voltage source, a memory cell disposed at the cross point of a word line and a bit line being selected by selecting said word line and said bit line, wherein the improved memory device further comprises charging circuit means, operatively connected in parallel with said load circuits, for detecting the switching period when the potentials of all the word lines are at the potential level of a non-selected condition and for electrically charging all the bit lines during the switching period of word line potentials.
Claim 3
Dependent Claim
44 words
The memory device of claim 1, wherein said charging circuit means comprises gate circuit means for detecting the potential levels of all of said word lines and a plurality of charging transistors which are controlled by the output signal from said gate circuit means.
Claim 4
Dependent Claim
30 words
The memory device of claim 2, wherein said gate circuit means comprises a NOR gate having a plurality of input transistors and a load transistor connected to said input transistors.
Claim 5
Dependent Claim
23 words
The memory device of claim 2, wherein each of said charging transistors is connected parallel to a corresponding one of said load circuits.
Claim 6
Dependent Claim
47 words
The memory device of claim 2, wherein each of said word lines has a beginning portion and an end portion, and wherein said gate circuit means comprises means for detecting the potential levels at the beginning portion and the end portion of each of said word lines.
Claim 7
Dependent Claim
67 words
The memory device of claim 5, wherein said gate circuit means comprises a NOR gate having a plurality of input transistors numbering double the number of said word lines, and a load transistor, each of said input transistors being connected between one of the beginning portion of a word line and said load transistor and between the end portion of a word line and said load transistor.
Claim 8
Dependent Claim
45 words
A memory device of claim 1, 2, 3, 4, 5, or 6, wherein each of said memory cells is a flip-flop type memory cell comprising a pair of cross coupled MIS transistors, a pair of transfer gate MIS transistors and a pair of load resistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-20 | 1987-08-22 | 1988-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-20 | 1991-08-22 | 1992-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-20 | 1995-08-22 | 1996-02-21 | $7700.00 | Window Closed / Lapsed |