Patent US4432133A successfully refreshed from Google Patents.
US4432133A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of producing a field effect transistor
Assignee: Fujitsu Ltd
•
Filing: 1982-08-10
•
Granted: 1984-02-21
•
Expires: 2002-08-10
Abstract
Abstract A method for producing a MOSFET which includes the steps of forming a thick insulating layer having an inclined surface and surrounding the active region of a semiconductor substrate, forming a thin insulating layer on the active region, forming a gate electrode crossing the thin insulating layer and extending on the thick insulating layer, and forming a source region and a drain region in the active region in which method the step of forming the gate electrode includes the steps of forming a conductive layer on the thin insulating layer and thick insulating layer, forming a resist layer on the conductive layer selectively exposing the resist layer to an energy ray to define a gate electrode pattern area of which a portion above the inclined surface and above the end portions of the active region is wider than another portion above the middle portion of the active region developing the resist layer and selectively etching the conductive layer by using the developed resist layer as a mask.
Inventors
- 👤 Toshikazu Furuya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/60; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
168 words
A method of producing a field effect transistor including a semiconductor substrate having an active region with a middle portion and end portions, and a field region, comprising the steps of: (a) forming a thick insulating layer on the field region of the semiconductor substrate, the thick insulating layer having an inclined surface and surrounding the active region of the semiconductor substrate; (b) forming a thin insulating layer on the active region of the semiconductor substrate; (c) forming a gate electrode on the thin and thick insulating layers, the gate electrode formed on a portion of the thin insulating layer and extending onto the thick insulating layer, and having first portions and a second portion, the first portions lying above the end portions of the active region and having a larger width than of the second portion lying above the middle portion of the active region; and (d) forming a source region and a drain region in the active region by selectively introducing impurities into the active region.
Claim 2
Independent Claim
168 words
A method of producing a field effect transistor including a semiconductor substrate having an active region with a middle portion and end portions, and a field region, comprising the steps of: (a) forming a thick insulating layer on the field region of the semiconductor substrate, the thick insulating layer having an inclined surface and surrounding the active region of the semiconductor substrate; (b) forming a thin insulating layer on the active region of the semiconductor substrate; (c) forming a gate electrode on the thin and thick insulating layers, the gate electrode formed on a portion of the thin insulating layer and extending onto the thick insulating layer, and having first portions and a second portion, the first portions lying above the end portions of the active region and having a larger width than of the second portion lying above the middle portion of the active region; and (d) forming a source region and a drain region in the active region by selectively introducing impurities into the active region.
Claim 3
Dependent Claim
23 words
A method according to claim 1, wherein said step (c) of forming the gate electrode comprises forming the gate electrode of polycrystalline silicon.
Claim 4
Dependent Claim
37 words
A method according to claim 1, wherein said step (c) of forming the gate electrode comprises forming the gate electrode of a material selected from the group consisting of molybdenum, tungsten, titanium, tantalum, platinum, and silicides thereof.
Claim 5
Dependent Claim
124 words
A method according to claim 1, wherein said step (c) of forming the gate electrode comprises the substeps of: (i) forming a conductor layer on the thin insulating layer and the thick insulating layer; (ii) forming a resist layer on the conductor layer; (iii) forming a photomask on portions of the resist layer, having a mask pattern, the mask pattern crossing the active region and having end portions which are wider than the middle portion of the active region; (iv) exposing a portion of the resist layer which is not covered with the mask pattern to an energy ray passing through the photomask; (v) developing the resist layer; and (vi) selectively etching the conductor layer by using the developed resist layer as a mask.
Claim 6
Dependent Claim
20 words
A method according to claim 4, wherein said substep (ii) of forming the resist layer comprises forming a positive-type resist.
Claim 7
Dependent Claim
30 words
A method according to claim 4, wherein said exposing substep (iv) comprises using an energy ray selected from the group consisting of a light, an ultraviolet ray and an X-ray.
Claim 8
Dependent Claim
115 words
A method according to claim 1, wherein said step (c) of forming the gate electrode comprises the substeps of: (i) forming a conductor layer on the thin insulating layer and the thick insulating layer; (ii) forming a resist layer on the conductor layer; (iii) selectively exposing the resist layer to an energy ray of an electron beam to define a gate electrode pattern area of which a portion above the inclined surface and above the end portions of the active region is wider than the portion above the middle portion of the active region; (iv) developing the resist layer; and (v) selectively etching the conductive layer by using the developed resist layer as a mask.
Claim 9
Dependent Claim
20 words
A method according to claim 7, wherein said substep (ii) of forming the resist layer comprises forming a positive-type resist.
Claim 10
Independent Claim
172 words
A method for producing a field effect transistor in a semiconductor substrate having an active region with a middle portion and end portions and a field region, comprising the steps of: (a) forming a thick insulating layer on the field region of the semiconductor substrate, the thick insulating layer having an inclined surface and surrounding the active region of the semiconductor substrate; (b) forming a thin insulating layer on the active region of the semiconductor substrate; (c) forming a gate electrode on the thin and thick insulating layers, comprising the substeps of: (i) forming a conductor layer on the thin and thick insulating layers; (ii) selectively exposing the conductor layer to an energy ray to define a gate electrode area having a portion above the inclined surface and end portions of the active region that is wider than a portion above the middle portion of the active region; and (d) forming source and drain regions in the active region by selectively introducing impurities through the thin insulating layer into the active region.
Claim 11
Independent Claim
172 words
A method for producing a field effect transistor in a semiconductor substrate having an active region with a middle portion and end portions and a field region, comprising the steps of: (a) forming a thick insulating layer on the field region of the semiconductor substrate, the thick insulating layer having an inclined surface and surrounding the active region of the semiconductor substrate; (b) forming a thin insulating layer on the active region of the semiconductor substrate; (c) forming a gate electrode on the thin and thick insulating layers, comprising the substeps of: (i) forming a conductor layer on the thin and thick insulating layers; (ii) selectively exposing the conductor layer to an energy ray to define a gate electrode area having a portion above the inclined surface and end portions of the active region that is wider than a portion above the middle portion of the active region; and (d) forming source and drain regions in the active region by selectively introducing impurities through the thin insulating layer into the active region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-20 | 1987-08-22 | 1988-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-20 | 1991-08-22 | 1992-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-20 | 1995-08-22 | 1996-02-21 | $7700.00 | Window Closed / Lapsed |