Patent US4432008A successfully refreshed from Google Patents.
US4432008A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gold-doped IC resistor region
Assignee: Leland Stanford Junior University
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Filing: 1980-07-21
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Granted: 1984-02-14
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Expires: 2000-07-21
Abstract
Abstract Resistive elements of semiconductor devices and integrated circuits are reduced in size thereby allowing larger scale integration. Deep level dopants including impurities or crystalline lattice defects, or both, are formed in a low resistance doped region thereby increasing the resistance of a portion of the doped region. Resistive contacts and interconnects require less semiconductor surface area.
Inventors
- 👤 Ron Maltiel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:20
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D1/00; H10D1/40; H10D1/43; H10D1/47; H10D62/50; H10D62/53; H10D62/80; H10D62/83; H10D62/834; H10D84/00; H10D84/80; H10D84/811; H10D84/817; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/40; H10W44/00; H10W44/401; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/024; Y10S257/00; Y10S257/902
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
115 words
An integrated semiconductor field effect transistor and resistor comprising a semiconductor body having a major surface, a first doped source region and a second doped drain region formed in said body and abutting said surface, said first region being spaced from said second region, a gate contact between said first and second regions and insulatively spaced from said surface, a third region formed within one of said first and second regions and abutting said surface, said third region comprising deep level impurities and having a resistance which is higher than the resistance of said one of said first and second regions, and an electrically conductive material on said surface and contacting only said third region.
Claim 2
Dependent Claim
115 words
An integrated semiconductor field effect transistor and resistor comprising a semiconductor body having a major surface, a first doped source region and a second doped drain region formed in said body and abutting said surface, said first region being spaced from said second region, a gate contact between said first and second regions and insulatively spaced from said surface, a third region formed within one of said first and second regions and abutting said surface, said third region comprising deep level impurities and having a resistance which is higher than the resistance of said one of said first and second regions, and an electrically conductive material on said surface and contacting only said third region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-13 | 1987-08-15 | 1988-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-13 | 1991-08-15 | 1992-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-13 | 1995-08-15 | 1996-02-14 | $7700.00 | Window Closed / Lapsed |