US4430641A
Expired / Lapsed
US
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Charge-pump glitch filter
Assignee: Tektronix Inc
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Filing: 1981-05-11
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Granted: 1984-02-07
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Expires: 2001-05-11
Abstract
Abstract A circuit including a conventional digital-to-analog converter (DAC) and a charge pump for producing an analog representation of an input waveform defined by an input digital bit stream, the analog representation being relatively free of spurious aberrations usually present in the output of a conventional DAC. The charge pump and an associated integrator are used to produce a first approximation of the input waveform and the DAC and an associated detuned slew-rate filter are used to maintain the first approximation in long-term conformance with a more accurate second approximation. Spurious aberrations in the second approximation are integrated over several steps of the input bit stream, thereby minimizing their adverse impact on the relatively true first approximation.
Inventors
- 👤 Bruce K. Baur
- 👤 John R. Ollis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:58
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
211 words
A circuit for converting a digital input signal defining a series of unit changes in a digital value into an analog output signal representative of said value, said unit changes occurring at a predetermined maximum rate, said circuit comprising: (a) means responsive to said digital input signal for producing a first analog signal having an analog value representative of said digital value, and for changing said analog value in proportion to each change in said digital value; (b) a slew-rate filter responsive to said first analog signal, and having a slew rate substantially less than the maximum rate of unit change in said digital value, for integrating each change in said analog value over several periods of said digital input signal and for producing a second analog signal representative of said integrating change; (c) means also responsive to said digital input signal for producing a third analog signal representative of the direction and timing of each change in said digital value; and (d) means within said slew-rate filter for impressing said third analog signal onto said second analog signal to produce an analog output signal representative of the instantaneous sum of the integrating changes in said analog value and the direction and timing of the unit changes in said digital value.
Claim 2
Dependent Claim
211 words
A circuit for converting a digital input signal defining a series of unit changes in a digital value into an analog output signal representative of said value, said unit changes occurring at a predetermined maximum rate, said circuit comprising: (a) means responsive to said digital input signal for producing a first analog signal having an analog value representative of said digital value, and for changing said analog value in proportion to each change in said digital value; (b) a slew-rate filter responsive to said first analog signal, and having a slew rate substantially less than the maximum rate of unit change in said digital value, for integrating each change in said analog value over several periods of said digital input signal and for producing a second analog signal representative of said integrating change; (c) means also responsive to said digital input signal for producing a third analog signal representative of the direction and timing of each change in said digital value; and (d) means within said slew-rate filter for impressing said third analog signal onto said second analog signal to produce an analog output signal representative of the instantaneous sum of the integrating changes in said analog value and the direction and timing of the unit changes in said digital value.
Claim 3
Dependent Claim
70 words
The circuit of claim 1 wherein said slew-rate filter includes a limited-swing amplifier interconnected with an integrator, said amplifier being responsive to said first analog signal and said integrator having a summing node, and wherein said means within said slew-rate filter for impressing said third analog signal onto said second analog signal includes means for supplying said third analog signal and the output of said amplifier to said summing node.
Claim 4
Dependent Claim
24 words
The circuit of claim 1 wherein said slew rate is approximately one tenth the maximum rate of said unit changes in said digital value.
Claim 5
Dependent Claim
75 words
The circuit of claim 1 wherein said means for producing said third analog signal includes charge pump control means responsive to said digital input signal for producing first and second pump signals representative respectively of a unit change in a first and second direction in said digital value, and charge pump means responsive to said first and second pump signals for producing an analog signal representative of the direction and timing of each such change.
Claim 6
Dependent Claim
23 words
The circuit of claim 4 wherein said first and second pump signals comprise first and second current pulses of predetermined magnitude and duration.
Claim 7
Dependent Claim
35 words
The circuit of claim 5 wherein said first current pulse is positive for a unit change in said first direction and said second current pulse is negative for a unit change in said second direction.
Claim 8
Dependent Claim
177 words
A circuit responsive to a digital input signal defining a series of unit changes in a digital value for filtering undesirable aberrations from an analog signal produced by a digital-to-analog converter also responsive to said digital input signal, said circuit comprising: (a) a slew-rate filter responsive to said analog signal produced by said digital-to-analog convertor, and having a slew-rate substantially less than the maximum rate of unit changes in said digital value, for integrating each change in said analog signal over several periods of said digital input signal, and for producing a second analog signal representative of said integrating change; (b) means responsive to said digital input signal for producing a third analog signal representative of the direction and timing of each change in said digital value; and (c) means within said slew-rate filter for impressing said third analog signal onto said second analog signal to produce an analog output signal representative of the instantaneous sum of the integrating changes in said analog signal and the direction and timing of the unit changes in said digital value.
Claim 9
Dependent Claim
177 words
A circuit responsive to a digital input signal defining a series of unit changes in a digital value for filtering undesirable aberrations from an analog signal produced by a digital-to-analog converter also responsive to said digital input signal, said circuit comprising: (a) a slew-rate filter responsive to said analog signal produced by said digital-to-analog convertor, and having a slew-rate substantially less than the maximum rate of unit changes in said digital value, for integrating each change in said analog signal over several periods of said digital input signal, and for producing a second analog signal representative of said integrating change; (b) means responsive to said digital input signal for producing a third analog signal representative of the direction and timing of each change in said digital value; and (c) means within said slew-rate filter for impressing said third analog signal onto said second analog signal to produce an analog output signal representative of the instantaneous sum of the integrating changes in said analog signal and the direction and timing of the unit changes in said digital value.
Claim 10
Dependent Claim
74 words
The circuit of claim 7 wherein said slew-rate filter includes a limited-swing amplifier interconnected with an integrator, said amplifier being responsive to said analog signal produced by said digital-to-analog convertor and said integrator having a summing node, and wherein said means within said slew-rate filter for impressing said third analog signal onto said second analog signal includes means for supplying said third analog signal and the output of said amplifier to said summing node.
Claim 11
Dependent Claim
75 words
The circuit of claim 7 wherein said means for producing said third analog signal includes charge pump control means responsive to said digital input signal for producing first and second pump signals representative respectively of a unit change in a first and second direction in said digital value, and charge pump means responsive to said first and second pump signals for producing an analog signal representative of the direction and timing of each such change.
Claim 12
Dependent Claim
24 words
The circuit of claim 7 wherein said slew rate is approximately one tenth the maximum rate of said unit changes in said digital value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-06 | 1987-08-08 | 1988-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-06 | 1991-08-08 | 1992-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-06 | 1995-08-08 | 1996-02-07 | $7700.00 | Window Closed / Lapsed |