Patent US4430587A successfully refreshed from Google Patents.
US4430587A
Expired / Lapsed
US
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MOS Fixed delay circuit
Assignee: Conexant Systems LLC
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Filing: 1982-01-13
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Granted: 1984-02-07
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Expires: 2002-01-13
Abstract
Abstract A MOS time delay circuit including a MOS regulated voltage supply circuit for supplying a voltage proportional to a predetermined trigger voltage and a RC delay circuit having a first input connected to the regulated voltage supply circuit, and a second input connected to the signal input, and an output. The circuit also includes a variable trigger point inverter having an input connected to the output of the RC delay circuit, and signal output.
Inventors
- 👤 Mark R. Tennyson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:46
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
254 words
A MOS time delay circuit comprising: a signal input; a MOS regulated voltage supply circuit for supplying a voltage proportional to a predetermined trigger voltage; a RC delay circuit having a first input connected to said regulated voltage supply circuit, and a second input connected to said signal input, and an output; and a first variable trigger point inverter having an input connected to the output of said RC delay circuit, and an output comprising means for supplying a relatively positive first and a relatively negative second source of electric potential to said circuit; a first depletion mode FET having one conduction path terminal connected to said first source of electric potential, the other conduction path terminal connected to a first intermediate node, at its control terminal connected to said first intermediate node; a first enhancement mode FET having one conduction path terminal connected to said first intermediate node, the other conduction path terminal connected to a second intermediate node, and its control terminal connected to the output of said RC delay circuit; a second enhancement mode FET having one conduction path terminal connected to said second intermediate node, the other conduction path terminal connected to said second source of potential, and its control electrode connected to said output of said RC delay circuit; and a second depletion mode FET having one conduction path terminal connected to said first source of electrical potential, the other conduction path terminal connected to said second intermediate node, and its control terminal connected to said second intermediate node.
Claim 2
Dependent Claim
254 words
A MOS time delay circuit comprising: a signal input; a MOS regulated voltage supply circuit for supplying a voltage proportional to a predetermined trigger voltage; a RC delay circuit having a first input connected to said regulated voltage supply circuit, and a second input connected to said signal input, and an output; and a first variable trigger point inverter having an input connected to the output of said RC delay circuit, and an output comprising means for supplying a relatively positive first and a relatively negative second source of electric potential to said circuit; a first depletion mode FET having one conduction path terminal connected to said first source of electric potential, the other conduction path terminal connected to a first intermediate node, at its control terminal connected to said first intermediate node; a first enhancement mode FET having one conduction path terminal connected to said first intermediate node, the other conduction path terminal connected to a second intermediate node, and its control terminal connected to the output of said RC delay circuit; a second enhancement mode FET having one conduction path terminal connected to said second intermediate node, the other conduction path terminal connected to said second source of potential, and its control electrode connected to said output of said RC delay circuit; and a second depletion mode FET having one conduction path terminal connected to said first source of electrical potential, the other conduction path terminal connected to said second intermediate node, and its control terminal connected to said second intermediate node.
Claim 3
Dependent Claim
182 words
A time delay circuit as defined in claim 1, wherein said MOS reguated voltage supply circuit comprises: means for supplying a relatively positive first and a relatively negative second source of electrical potential to said circuit; a second variable trigger point inverter having an input and an output; a first depletion mode FET having one conduction path terminal connected to said first source of electric potential, the other conduction path terminal connected to said first input of said RC delay circuit, and its control terminal connected to the output of said second variable trigger inverter; a second depletion FET having one conduction path terminal connected to said input of said RC delay circuit, the other conduction path terminal connected to a first intermediate node, and its control terminal connected to said input of said RC input circuit; a third depletion FET having one conduction path terminal connected to the first intermediate node, said second other path terminal connected to said second source of electric potential, control terminal connected to the input of said second variable trigger inverter and said first intermediate node.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-06 | 1987-08-08 | 1988-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-06 | 1991-08-08 | 1992-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-06 | 1995-08-08 | 1996-02-07 | $7700.00 | Window Closed / Lapsed |