Patent US2424256A successfully refreshed from Google Patents.
Patent US4430584A successfully refreshed from Google Patents.
US4430584A
Expired / Lapsed
US
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Modular input/output system
Assignee: Texas Instruments Inc
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Filing: 1980-05-29
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Granted: 1984-02-07
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Expires: 2000-05-29
Abstract
Abstract A memory mapped I/O scheme treats each I/O buffer as a memory element which can be addressed, written into or read from. Each I/O buffer has its own memory address decoder which eliminates the need for special select/control lines for each buffer and enables the use of a single address/data bus. Thus redesign and reconfiguration of the I/O buffers is more easily accomplished because it does not require new select/control lines to be laid out when buffer locations are changed.
Inventors
- 👤 Ashok H. Someshwar
- 👤 Kenneth A. Lies
- 👤 Jeffrey R. Teza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:59
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
118 words
An integrated circuit coupled to means external to said integrated circuit including a plurality of coupling elements comprising: (i) bus means for providing an address signal and a data signal, (ii) interconnect means coupled to said bus means comprising a plurality of individual amplifiers for isolating, amplifying and re-outputting a received data signal in response to receiving a decode signal and a plurality of individual decoders each coupled to a corresponding amplifier for providing a decode signal in response to a particular address signal, said interconnect means selectively coupling the received data signal to a corresponding one of said coupling elements in response to decoding a particular address signal defined prior to its reception by said interconnect means.
Claim 2
Dependent Claim
118 words
An integrated circuit coupled to means external to said integrated circuit including a plurality of coupling elements comprising: (i) bus means for providing an address signal and a data signal, (ii) interconnect means coupled to said bus means comprising a plurality of individual amplifiers for isolating, amplifying and re-outputting a received data signal in response to receiving a decode signal and a plurality of individual decoders each coupled to a corresponding amplifier for providing a decode signal in response to a particular address signal, said interconnect means selectively coupling the received data signal to a corresponding one of said coupling elements in response to decoding a particular address signal defined prior to its reception by said interconnect means.
Claim 3
Dependent Claim
18 words
The integrated circuit of claim 1 wherein each individual amplifier may be interchanged with any other individual amplifier.
Claim 4
Dependent Claim
18 words
The integrated circuit of claim 1 wherein each individual decoder may be interchanged with any other individual decoder.
Claim 5
Dependent Claim
25 words
The integrated circuit of claim 1 wherein each individual decoder is individually programmable so as to be responsive to a particular programmed predefined address signal.
Claim 6
Dependent Claim
23 words
The integrated circuit of claim 1 wherein the interconnect means includes a programmable interconnect contact matrix so as to define a desired pinout.
References Cited (Backward Citations)
US4040029A
Cited
US4286321A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-06 | 1987-08-08 | 1988-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-06 | 1991-08-08 | 1992-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-06 | 1995-08-08 | 1996-02-07 | $7700.00 | Window Closed / Lapsed |