Memory system with reduced block decoding

Claim 2

In a memory system comprising a plurality of memory module means for storing blocks of data, each memory module means including word address decoding means for selecting a word stored in said memory module means and enabling means for reading out from said memory module means the word selected by said word address decoding means, the improvement comprising: a separate block address decoding means included in each one of said plurality less one of said memory module means for producing an output signal to the enabling means of its associated memory module means; means responsive to the output signals from said block address decoding means for producing a select signal when none of said plurality less one of said memory module means is enabled; and means for coupling said select signal to the enabling means of said one of said memory module means to enable said one of the memory module means when none of said plurality less one of said memory module means is enabled.

Claim 3

In a memory system including m address line means partitioned into k select line means, n block address line means, and w word address line means, where k + n + w = m, a first plurality of memory module means, including block address decoder means responsive to said n block address line means for enabling an addressed one of said first plurality of memory module means and word address decoder means responsive to at least a subset of said w word address line means for selecting a word location within one of said first plurality of memory module means, for storing data, the improvement comprising: means included in said first plurality of memory module means, responsive to said block address decoder means, for producing enabled output signals when one of said first plurality of memory module means is enabled; a second plurality of memory module means each having an enabling input means and word address decoder means responsive to at least a subset of said w word address line means for selecting a word location therein, for storing data; and activating means responsive to said k select line means and to said enabled output signals for supplying an enabling signal to the enabling input means of one of said second plurality of memory module means when none of said first plurality of memory module means is addressed.

Claim 4

In a memory system including m address line means partitioned into k select line means, n block address line means, and w word address line means, where k + n + w = m, a first plurality of memory module means, including block address decoder means responsive to said n block address line means for enabling an addressed one of said first plurality of memory module means and word address decoder means responsive to at least a subset of said w word address line means for selecting a word location within one of said first plurality of memory module means, for storing data, the improvement comprising: means included in said first plurality of memory module means, responsive to said block address decoder means, for producing enabled output signals when one of said first plurality of memory module means is enabled; a second plurality of memory module means each having an enabling input means and word address decoder means responsive to at least a subset of said w word address line means for selecting a word location therein, for storing data; and activating means responsive to said k select line means and to said enabled output signals for supplying an enabling signal to the enabling input means of one of said second plurality of memory module means when none of said first plurality of memory module means is addressed.

Claim 5

The invention as claimed in claim 2 wherein said activating means includes: decoding means, having at least 2 k output lines, responsive to said k select line means for producing a select signal on one of said 2 k output lines; first gating means responsive to said enabled output signals from the first plurality of memory module means for producing an output signal when none of said first plurality of memory module means is addressed; and second gating means, each having an output means coupled to the enabling input means of a different one of said second plurality of memory module means and responsive to a different one of said 2 k output lines and to the output signal from said first gating means for producing an enabling signal to the enabling input means of a corresponding one of said second plurality of memory module means.