Patent US4428042A successfully refreshed from Google Patents.
US4428042A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interface device for coupling a system of time-division multiplexed channels to a data concentrator
Assignee: Siemens AG
•
Filing: 1981-02-04
•
Granted: 1984-01-24
•
Expires: 2001-02-04
Abstract
Abstract A coupling device provides for an inexpensive coupling between two data processing systems at a relatively low expense, even when a large number of channels is involved. The coupling device provides, for each data processing system, a clock pulse line, a transmitting bus, a receiving bus and an address bus. For each address, two memory cells are provided and have associated address decoders. The address decoders receive the addresses by way of the address buses and with identification of an associated address, transmit decoding signals to the memory cells. A pair of clock pulse controls provide sequences of write commands and read commands for controlling the writing of individual bits of the two transmitting buses into the addressed memory cells and cause transfer of these bits to the receiving buses.
Inventors
- 👤 Dieter Niethhammer
- 👤 Robert Eggertsberger
- 👤 Gerhard Wilmers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:32
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/16; H04J3/1682; H04L; H04L12/00; H04L12/50; H04L12/52; H04L12/525
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
332 words
A coupling device for coupling a time-division multiplex system to a concentrator of a data processing system, comprising: a first data transmission bus, a first address bus, a first data receiving bus and a first clock line in the area of the time-division multiplex system; a second data transmission bus, a second address bus, a second data receiving bus and a second clock line in the area of the concentrator; a plurality of first memory cells in the coupling device wherein a first memory cell is provided for each address of the first address bus; a plurality of second memory cells in the coupling device wherein a second memory cell is provided for each address of the second address bus; a group of said first memory cells connected by way of their data inputs to said second data transmission bus and by way of their data outputs to said second data receiving bus; a group of said second memory cells connected by way of their data inputs to said second data transmission bus and by way of their data outputs to said first data receiving bus; a plurality of first address decoders and a plurality of second address decoders, said first group of memory cells and said second group of memory cells respectively connected to said first and second address decoders; said first and second address decoders connected to said first and second address buses, respectively; a first clock control and a second clock control respectively connected to said first and second clock lines, said first and second clock controls generating sequences of first and second write instructions, respectively, with which data appearing on said first and second data transmission buses, respectively, are transferred as addresses into said memory cells of said first and second groups of memory cells, respectively, and said first and second clock controls further operable to generate sequences of first and second read instructions for reading data from said memory cells of said first and second groups, respectively.
Claim 2
Dependent Claim
332 words
A coupling device for coupling a time-division multiplex system to a concentrator of a data processing system, comprising: a first data transmission bus, a first address bus, a first data receiving bus and a first clock line in the area of the time-division multiplex system; a second data transmission bus, a second address bus, a second data receiving bus and a second clock line in the area of the concentrator; a plurality of first memory cells in the coupling device wherein a first memory cell is provided for each address of the first address bus; a plurality of second memory cells in the coupling device wherein a second memory cell is provided for each address of the second address bus; a group of said first memory cells connected by way of their data inputs to said second data transmission bus and by way of their data outputs to said second data receiving bus; a group of said second memory cells connected by way of their data inputs to said second data transmission bus and by way of their data outputs to said first data receiving bus; a plurality of first address decoders and a plurality of second address decoders, said first group of memory cells and said second group of memory cells respectively connected to said first and second address decoders; said first and second address decoders connected to said first and second address buses, respectively; a first clock control and a second clock control respectively connected to said first and second clock lines, said first and second clock controls generating sequences of first and second write instructions, respectively, with which data appearing on said first and second data transmission buses, respectively, are transferred as addresses into said memory cells of said first and second groups of memory cells, respectively, and said first and second clock controls further operable to generate sequences of first and second read instructions for reading data from said memory cells of said first and second groups, respectively.
Claim 3
Dependent Claim
61 words
The device of claim 1, wherein said first and second clock pulse controls include means operable to respectively produce first and second write commands and clock pulse signals including predetermined pulse edges which coincide with the write commands, and first and second read commands generated after the respective write commands when the respective clock pulse signal is a predetermined binary value.
Claim 4
Dependent Claim
136 words
A coupling device of claim 1, further comprising, a first group of buffer memories connecting said first transmitting bus and said first address bus, respectively, to said first group of memory cells; a second group of buffer memories connecting said second transmitting bus and said second address bus, respectively, to said second group of memory cells; said first group of buffer memories and said second group of buffer memories, respectively, controlled with a first memory signal and a second memory signal, respectively, which coincides with pulse edges of said first and second clock pulse signals, respectively; and the sequence of said first and second write commands, respectively, is generated after the appearance of said first and second memory signals, respectively and simultaneously with a preset binary value of said second and first clock pulse signals, respectively.
Claim 5
Dependent Claim
240 words
The device of claim 1, and further comprising: a third group of memory cells each including a data input and a data output; a test signal bus connected to said data inputs of said third group of memory cells; a test loop control stage connected to said data outputs of said third group of memory cells, said data outputs also connected to the decoding lines of said first and second groups of memory cells, respectively; a pair of switches each including a first switch position connecting said second transmitting bus with said data inputs of said second group of memory cells and the data outputs of said first group of memory cells with said second receiving bus and, respectively, connecting said first transmitting bus with the data inputs of said first group of memory cells and said data outputs of said second group of memory cells with said first receiving bus, and a second switch position connecting said data outputs of said first group of memory cells via said test loop to said data inputs of said second group of memory cells and, respectively, connecting said data outputs of said second group of memory cells via said test loop to said data inputs; and a test loop control stage responsive to the lack of a test signal or to the presence of a test signal, to selectively set said first and second switches in said first and second switch positions.
References Cited (Backward Citations)
US3639694A
Cited
US4106091A
Cited
US4065862A
Cited
US4271480A
Cited
US4047246A
Cited
US4298928A
Cited
US4205373A
Cited
US4328559A
Cited
US4291370A
Cited
US4347601A
Cited
US4309754A
Cited
US4312066A
Cited
US4347582A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-23 | 1987-07-25 | 1988-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-23 | 1991-07-25 | 1992-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-23 | 1995-07-25 | 1996-01-24 | $7700.00 | Window Closed / Lapsed |