Differential amplifier stage having bias compensating means

Claim 1

In an amplifier of the type comprising at least two input terminals and a differential pair of transistors, at least one input terminal being adapted to receive an input signal and said differential pair of transistors including first and second bipolar transistors, said first transistor being coupled to system ground, wherein the improvement comprises: bipolar transistor means comprising a third bipolar transistor having a base, emitter and collector, said base of said third transistor being coupled to said one input terminal and said emitter of said third transistor being coupled to said second transistor so as to buffer said one input terminal from said differential pair; and compensation means for generating a compensating current to said bipolar transistor means, said collector of said third bipolar transistor being coupled to said compensation means so as to operate as an emitter follower, said compensation means comprising fourth, fifth and sixth bipolar transistors, each of said fourth, fifth and sixth transistors having a base, collector and emitter, said base of said fourth transistor being coupled to the base of said third transistor, said collector of said fourth transistor being coupled to system ground and said emitter of said fourth transistor being coupled to the collector of said sixth bipolar transistor, said emitter of said fifth transistor being coupled to the collector of said third bipolar transistor and said collector of said fifth transistor being coupled to a predetermined voltage source; and said emitter of said sixth bipolar transistor is adapted to be coupled to a preselected voltage source; and means for reducing DC voltage offset between the bases of said differential pair, said means for reducing said voltage offset comprising diode means coupled to the emitter of said first transistor, a first resistance means coupling said diode means to a junction point, and a second resistance means coupling the emitter of said second transistor to said junction point, wherein the values of said first and second resistors are set to reduce the noise through said differential pair; wherein said bipolar transistor means and said compensation means are adapted to reduce the amount of bias signal drawn from said input signal by said differential pair than would be otherwise drawn by said differential pair if said one input terminal were directly connected to said differential pair.