Integrated circuit amplifier having an improved gain-versus-frequency characteristic

Claim 2

An amplifier having an input stage, with said input stage including, in combination: a. a first input semiconductor device having input, output, and common electrodes, b. a second input semiconductor devine having input, output and common electrodes, and c. pole compensating capacitance means in the order of 10 picofarads connected to the common electrodes of both said first and second input semiconductor devices for relocating a pole of the transfer function of said amplifier to thereby improve the gain-versus-frequency characteristic of said amplifier.

Claim 3

The amplifier defined in claim 1 wherein said pole compensating capacitance means includes a single capacitor directly connected between the common electrodes of said first and second input semiconductor devices for broadbanding said pole of said amplifier''s transfer function.

Claim 4

The amplifier defined in claim 1 wherein said pole compensating capacitance means includes first and second capacitors connected, respectively, to the common electrodes of said first and second input semiconductor devices for bypassing common electrode resistances of said first and second semiconductor devices at high frequencies and thus improving the high frequency response of said amplifier.

Claim 5

The amplifier defined in claim 1 which further includes an output transistor stage having another pole compensating capacitance means therein so that the size of said another pole compensating capacitance means can be reduced to a value of capacitance in the order of 15 picofarads by the inclusion of said pole compensating capacitance means in said input stage of said amplifier, and the total circuit capacitance of said amplifier maintained at an absolute minimum.

Claim 6

The amplifier defined in claim 4 wherein said output stage includes: a. a first output transistor, b. a second output transistor cascaded to said first output transistor, and c. said another pole compensating capacitance means in said output stage connected between the output of said second output transistor and the input of said first output transistor to split two of the poles of said amplifiers''s transfer function.

Claim 7

An amplifier having an input stage, with said input stage including, in combination: a. a first input transistor having input, output and common electrodes, b. a second input transistor having input, output, and common electrodes, and c. pole compensating capacitance means in the order of 10 picofarads connected to the common electrodes of both said first and second input transistors for relocating a pole of the transfer function of said amplifier to thereby improve the gain-versus-frequency characteristic of said amplifier.

Claim 8

An amplifier having an input stage, with said input stage including, in combination: a. a first input transistor having input, output and common electrodes, b. a second input transistor having input, output, and common electrodes, and c. pole compensating capacitance means in the order of 10 picofarads connected to the common electrodes of both said first and second input transistors for relocating a pole of the transfer function of said amplifier to thereby improve the gain-versus-frequency characteristic of said amplifier.

Claim 9

The amplifier defined in claim 6 wherein said pole compensating capacitance means includes a single capacitor directly connected between the common electrodes of said first and second input transistor for broadbanding said pole of said amplifier''s transfer function.

Claim 10

The amplifier defined in claim 6 wherein said pole compensating capacitance means includes first and second capacitors connected, respectively, to the common electrodes of said first and second input transistors for bypassing common electrode resistances of said first and second transistors at high frequencies and thus improving the high frequency response of said amplifier.

Claim 11

The amplifier defined in claim 6 which Further includes an output transistor stage having another pole compensating capacitance means therein so that the size of said another pole compensating capacitance means can be reduced to a value of capacitance in the order of 15 picofarads by the inclusion of said pole compensating capacitance means in said input stage of said amplifier, and the total circuit capacitance of said amplifier maintained at an absolute minimum.

Claim 12

The amplifier defined in claim 9 wherein said output stage includes: a. a first output transistor, b. a second output transistor cascaded to said first output transistor, and c. said another pole compensating capacitance means in said output stage connected between the output of said second output transistor and the input of said first output transistor to split two of the poles of said amplifier''s transfer function.

Claim 13

The amplifier defined in claim 10 wherein said pole compensating capacitance means includes a single capacitor directly connected between the common electrodes of said first and second input transistors for broadbanding said pole of said amplifier''s transfer function.

Claim 14

The amplifier defined in claim 11 which further includes first and second degeneration resistors serially connected between said common electrodes of said first and second input transistors and connected in parallel with said pole compensating capacitance means in said input stage for stabilizing said amplifier.

Claim 15

The amplifier defined in claim 10 wherein said pole compensating capacitance means includes first and second capacitors connected respectively to the common electrodes of said first and second input transistors for bypassing common electrode resistances of said first and second transistors at high frequencies and thus improving the high frequency response of said amplifier.

Claim 16

The amplifier defined in claim 13 which further includes first and second degeneration resistors connected in parallel with said first and second capacitors for swamping the internal transistor emitter resistances of said first and second input transistors and thereby temperature stabilizing said amplifier.

Claim 17

The amplifier defined in claim 14 which further includes third and fourth output transistors coupled to said first and second capacitors and adapted to provide an output signal for said input stage for driving said output stage of said amplifier.

Claim 18

The amplifier defined in claim 15 which further includes: a. a first resistive-transistor bias string connected between first and second power supply terminals and connected to said input stage for DC biasing said input stage with predetermined operating potentials, and b. a second resistive-transistor bias string connected between first and second power supply terminals and further connected to said output stage for DC biasing said output stage with predetermined operating potentials.

Claim 19

An amplifier having an input stage with a high impedance output node, said input stage including, in combination: a. a first input semiconductor device having input, output and common electrodes; b. a second input semiconductor device having input, output and common electrodes; c. first and second resistive elements coupled between different ones of said common electrodes and a reference potential; and d. pole compensating capacitance means connected to the common electrodes of both said first and second input semiconductor devices for cancelling the effects of the first dominant pole of said input stage existing at said high impedance output node, the value of the capacitance, Cz, effectively between said common electrodes being chosen such that its effect on the output of said input stage is to cause the decrease in the output at said high impedance output node due to the occurrence of said first dominant pole to be cancelled by augmenting the gain of said input stage by exactly the amount of said decrease, said first dominant pole being at tHe natural frequency of the RC circuit formed by the inherent parasitic capacitance and the inherent resistance between said high impedance output node and AC ground, whereby the effect of said first dominant pole in reducing the output of said input stage above said natural frequency is nullified thereby extending the frequency response of said amplifier, said capacitance value being determined by the values of said first and second resistors, said parasitic capacitance and said parasitic resistance, such that whenever the values of said first and second resistors are R1 and R2 respectively, whenever said parasitic capacitance has a value Cp and the parasitic resistance between said high impedance node and AC ground has a value Rp, then said capacitance value Cz is chosen to be such that where f is said natural frequency and is determined for a given input stage by determining the frequency at which the output at said high impedance node begins said decrease, whereby determination of the actual values of Cp and Rp are unnecessary in the determination of the capacitance value, Cz, of said pole compensating capacitance means.

Claim 20

An amplifier having an input stage with a high impedance output node, said input stage including, in combination: a. a first input semiconductor device having input, output and common electrodes; b. a second input semiconductor device having input, output and common electrodes; c. first and second resistive elements coupled between different ones of said common electrodes and a reference potential; and d. pole compensating capacitance means connected to the common electrodes of both said first and second input semiconductor devices for cancelling the effects of the first dominant pole of said input stage existing at said high impedance output node, the value of the capacitance, Cz, effectively between said common electrodes being chosen such that its effect on the output of said input stage is to cause the decrease in the output at said high impedance output node due to the occurrence of said first dominant pole to be cancelled by augmenting the gain of said input stage by exactly the amount of said decrease, said first dominant pole being at tHe natural frequency of the RC circuit formed by the inherent parasitic capacitance and the inherent resistance between said high impedance output node and AC ground, whereby the effect of said first dominant pole in reducing the output of said input stage above said natural frequency is nullified thereby extending the frequency response of said amplifier, said capacitance value being determined by the values of said first and second resistors, said parasitic capacitance and said parasitic resistance, such that whenever the values of said first and second resistors are R1 and R2 respectively, whenever said parasitic capacitance has a value Cp and the parasitic resistance between said high impedance node and AC ground has a value Rp, then said capacitance value Cz is chosen to be such that where f is said natural frequency and is determined for a given input stage by determining the frequency at which the output at said high impedance node begins said decrease, whereby determination of the actual values of Cp and Rp are unnecessary in the determination of the capacitance value, Cz, of said pole compensating capacitance means.