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US4423434A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having two or more semiconductor elements with paired characteristics regularly arranged in a semiconductor substrate

Assignee: Toshiba Corp
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Filing: 1980-12-03
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Granted: 1983-12-27
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Expires: 2000-12-03
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Abstract

Abstract Semiconductor elements are arranged in a semiconductor substrate substantially equidistantly of a dicing line and oriented in the same direction. A region where the semiconductor elements are regularly arranged is the one where, when the semiconductor substrate and a semiconductor element are integrally formed with a sealing member, a characteristic of the semiconductor element abruptly changes, ranging from the center line of the dicing line to a point having stress of 90% of the stress developed in the center area of the semiconductor substrate or ranging from the center line of the dicing line to a point distanced from the center line by a distance 1.8 times the thickness of the semiconductor substrate or less. The semiconductor substrate with semiconductor elements arranged therein is integrally formed by a sealing member.

Inventors

  • 👤 Shigeru Komatsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 03:45
CPC Classifications
H; H10; H10N; H10N39/00; H10D; H10D89/00; H10D89/10; Y; Y10; Y10S; Y10S257/00; Y10S257/925

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 80 words
In a semiconductor device, the improvement comprising: a semiconductor substrate; at least two semiconductor elements with paired characteristics disposed equidistantly from an edge of said semiconductor substrate with the same orientation with respect to each other in said semiconductor substrate, wherein said semiconductor elements are disposed within an area defined by said edge of said semiconductor substrate and by a line which is separated from said edge by a distance 1.8 times the thickness of said semiconductor substrate or less.
Claim 2
Dependent Claim 80 words
In a semiconductor device, the improvement comprising: a semiconductor substrate; at least two semiconductor elements with paired characteristics disposed equidistantly from an edge of said semiconductor substrate with the same orientation with respect to each other in said semiconductor substrate, wherein said semiconductor elements are disposed within an area defined by said edge of said semiconductor substrate and by a line which is separated from said edge by a distance 1.8 times the thickness of said semiconductor substrate or less.
Claim 3
Dependent Claim 27 words
A semiconductor device according to claim 1, wherein said semiconductor substrate has a surface of {1, 0, 0} and said semiconductor elements are arranged in said surface.
Claim 4
Dependent Claim 27 words
A semiconductor device according to claim 1 further comprising: a sealing member for integrally sealing said semiconductor substrate and said semiconductor elements disposed in said semiconductor substrate.
Claim 5
Dependent Claim 13 words
A semiconductor device according to claim 3, wherein said sealing member is resin.

References Cited (Backward Citations)

GB1236401A Cited
US4025941A Cited
GB1514180A Cited
US3965452A Cited
US4236832A Cited
JPS55125661A Cited
US4268848A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-12-26 1987-06-27 1987-12-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-12-26 1991-06-27 1991-12-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-12-26 1995-06-27 1995-12-27 $7700.00 Window Closed / Lapsed

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