Binary MOS switched-carry parallel adder

Claim 1

A monolithic integrated n-stage parallel adder for two numbers each represented in an n-digit binary code, where n is an integer greater than one, each stage of said adder employing enhancement-mode insulated-gate field-effect transistors of the same conductivity type and having a carry signal switched therethrough by an electronic changeover switch, each of said n+stages comprising: a first EXCLUSIVE-OR block including a first AND gate having two inputs each receiving a different one of an associated digit of said two numbers, a second AND gate having two inputs each receiving a different one of an inverse of said associated digit of said two numbers and a first NOR gate having two inputs each coupled to an output of a different one of said first and second AND gates; a second EXCLUSIVE-OR block including third and fourth AND gates each having a first input coupled to the output of said first NOR gate and a second input coupled to a carry signal output of the next lower-order stage of said n+stages and a second NOR gate having two inputs each coupled to an output of a different one of said third and fourth AND gates to provide a sum signal for its associated one of said n+stages; an ON/OFF transistor switch or said changeover switch having its controlled current path coupled between the output of an inverter coupled to said carry signal output of the next lower-order stage of said n+stages and a carry signal output of said associated one of said n+stages and a gate coupled to the output of said first NOR gate, said inverter in the lowest-order stage of said n+stages being replaced by a NAND block to combine said associated digits of said two numbers; a first switching transistor having its controlled current path coupled between said carry signal output of said associated one of said n+stages and a first terminal of a power supply; a second, depletion mode switching transistor having its controlled current path coupled between said carry signal output of said associated one of said n+stages and a second terminal of said power supply; a first NOR block having two inputs each receiving a different one of said associated digits of said two numbers and an output coupled to a gate of one of said first and second switching transistors; and a second NOR block having two inputs each receiving a different one of said inverse of said associated digit of said two numbers and an output coupled to a gate of the other of said first and second switching transistors.