Sense amplification scheme for random access memory

Claim 1

For use in a capacitive storage integrated circuit memory device having at least one sense amplifier of a type employing a latch including cross-coupled field effect transistors with common source electrodes, said sense amplifier for sensing and comparing charge on a bit line coupled to each drain electrode of each one of said transistors of said latch, each said bit line being selectively coupled to a storage cell through a transistor switch transfer gate in response to signals applied to a word line, an apparatus for controlling sense rate of said bit lines comprising: means operative to sense said word line signals for initiating a clock sequence, said clock sequence initiating means producing a first output signal having a first dynamic characteristic which is delayed relative to said word line signals; first clock means responsive to said first output signal for generating a second output signal having a second dynamic characteristic which is delayed relative to said first output signal; second clock means responsive to said second output signal for generating a third output signal having a third dynamic characteristic which is delayed relative to said second output signal and which overlaps in time said second output signal; and means operative to amplify current in proportion to at least said second output signal and to said third output signal and to sum said amplified current for applying current in a controlled manner to said common source electrodes to strobe said source electrodes at a controlled sense rate.