US4420722A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testing semiconductor furnaces for heavy metal contamination
Assignee: Intersil Corp
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Filing: 1980-11-14
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Granted: 1983-12-13
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Expires: 2000-11-14
Abstract
Abstract A technique for testing for heavy metal contamination in semiconductor processing furnaces includes use of a chip having a plurality of PN- junctions, at least one of which is completely isolated from the sides of the chip. The chip is manufactured to exhibit a high reverse recovery time and this can be conveniently accomplished by a combination of a gettering layer to getter the heavy metal atoms away from the junction and by never raising the temperature of the chip above 800° C. after the gettering layer is provided. In use, the chip is fed through a furnace either with or, preferably before the wafers being processed, which is operating at the conditions under which semiconductor devices are to be processed. After the chip is removed from the furnace, its reverse recovery time is measured and compared to its initial reverse recovery time to determine if it has decreased.
Inventors
- 👤 Albert A. Todd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:45
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; G; G01; G01N; G01N27/00; G01N27/26; G01N27/403; G01N27/414
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
166 words
A method of testing a semiconductor processing furnace for heavy metal contamination, said method comprising: providing a chip of semiconductor material having first and second major surfaces, an outer N+ region extending into said chip from the first major surface, an intermediate N- region extending into said chip from the second major surface, a plurality of outer P regions extending into said chip from the second major surface so as to form a plurality of junctions with the N- intermediate region, and an N+ isolation region extending into said chip from the second major surface, said N+ isolation region being located between the P regions so as to electrically isolate the P regions from each other and from the side surface of the chip; conveying said chip through the furnace to be tested while the furnace is operating under normal processing conditions; measuring the reverse recovery time of said chip after it is withdrawn from said furnace; and determining if the reverse recovery time has decreased.
Claim 2
Independent Claim
166 words
A method of testing a semiconductor processing furnace for heavy metal contamination, said method comprising: providing a chip of semiconductor material having first and second major surfaces, an outer N+ region extending into said chip from the first major surface, an intermediate N- region extending into said chip from the second major surface, a plurality of outer P regions extending into said chip from the second major surface so as to form a plurality of junctions with the N- intermediate region, and an N+ isolation region extending into said chip from the second major surface, said N+ isolation region being located between the P regions so as to electrically isolate the P regions from each other and from the side surface of the chip; conveying said chip through the furnace to be tested while the furnace is operating under normal processing conditions; measuring the reverse recovery time of said chip after it is withdrawn from said furnace; and determining if the reverse recovery time has decreased.
Claim 3
Dependent Claim
20 words
A method in accordance with claim 1 wherein the reverse recovery time is measured across said one of said junctions.
Claim 4
Dependent Claim
126 words
A test device for use in monitoring heavy metal contamination in a semiconductor processing furnace, said device comprising a chip of semiconductor material having first and second major surfaces, an outer N+ region extending into said chip from the first major surface, an intermediate N- region extending into said chip from the second major surface, a plurality of outer P regions extending into said chip from the second major surface so as to form a plurality of junctions with the N- intermediate region, and an N+ isolation region extending into said chip from the second major surface, said N+ isolation region being located between the P regions so as to electrically isolate the P regions from each other and from the side surface of the chip.
Claim 5
Dependent Claim
126 words
A test device for use in monitoring heavy metal contamination in a semiconductor processing furnace, said device comprising a chip of semiconductor material having first and second major surfaces, an outer N+ region extending into said chip from the first major surface, an intermediate N- region extending into said chip from the second major surface, a plurality of outer P regions extending into said chip from the second major surface so as to form a plurality of junctions with the N- intermediate region, and an N+ isolation region extending into said chip from the second major surface, said N+ isolation region being located between the P regions so as to electrically isolate the P regions from each other and from the side surface of the chip.
Claim 6
Dependent Claim
27 words
A test device in accordance with claim 3 wherein said outer N+ region and outer P regions are relatively thin and said intermediate region is relatively thick.
Claim 7
Dependent Claim
30 words
A test device in accordance with claim 3 wherein said N+ isolation region extends from said second major surface to a depth greater than that of said outer P regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-12 | 1987-06-13 | 1987-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-12 | 1991-06-13 | 1991-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-12 | 1995-06-13 | 1995-12-13 | $7700.00 | Window Closed / Lapsed |