Semiconductor device and manufacturing process thereof

Claim 2

A process for manufacturing a field effect transistor in a semiconductor wafer including a semiconductor region having a first conductivity type and a low impurity concentration, which process comprises the steps of: (a) forming, on one surface of said semiconductor region, a double-mask layer from a first film and a second film superposed on said first film, and having an aperture formed through said double-mask layer; (b) diffusing an impurity element of a predetermined first conductivity type into said semiconductor region through said aperture to form a diffused region having said first conductivity type and a predetermined impurity concentration; (c) selectively etching said first film through said aperture and widening at least partially the aperture on said first film, thereby obtaining a new aperture on said first film; (d) diffusing an impurity element of a second conductivity type opposite to said first conductivity type into said semiconductor region through said new aperture to form a gate of said transistor having second conductivity type and a high impurity concentration, and controlling the diffusion in this step so that said gate has a depth less than that of said diffused region, said new aperture being formed during said step (c) having a dimension such that said gate surrounds a predetermined region, which is a current channel of said transistor, of said first semiconductor layer at a predetermined portion of said gate, and that a portion of the gate exclusive of said predetermined portion thereof overlaps a portion of said diffused region; and (e) forming, at one end of said current channel, a drain for said transistor having said first conductivity type.

Claim 3

The process according to claim 1 wherein said step (e) comprises the steps of: after said step (d), unmasking said one end portion of said current channel to be exposed, and thereafter diffusing an impurity element of said first conductivity type into said unmasked one end portion to form a diffused region to serve as said drain.

Claim 4

The process according to claim 1 wherein said impurity element employed in said step (b) has said first conductivity type, and the diffusion in said step (b) is controlled so that said diffused region has a high impurity concentration.

Claim 5

A process for manufacturing an integrated semiconductor device including a bipolar transistor and a field effect transistor formed in a single common semiconductor wafer comprising a semiconductor region having a first conductivity type and a low impurity concentration, which process comprises the steps of: (a) forming, on one surface of said semiconductor region, a double-mask layer made from a first film and a second film superposed on said first film and having apertures formed through said double-mask layer; (b) diffusing an impurity element of a predetermined first conductivity type into said semiconductor region through said apertures to form diffused regions have said first conductivity type and a predetermined impurity concentration; (c) selectively etching said first film through said apertures and widening at least partially said apertures on said first film, thereby obtaining new apertures on said first film; (d) diffusing an impurity element of a second conductivity type opposite to said first conducivity type into said semiconductor region through said new apertures to form an emitter of said bipolar transistor, a collector of said bipolar transistor, and a gate of said field effect transistor merged into said collector, and controlling the diffusion in this step so that said gate, emitter and collector have a depth less than that of said diffused regions, said new apertures being formed in said step (c) so as having dimensions such that said gate surrounds a predetermined region, which is defined as a current channel of said field effect transistor, of said semiconductor region at a predetermined portion of said gate, with a portion of the gate excluding said predetermined portion thereof overlapping a portion of at least one of said diffused regions, and that another predetermined region, which is defined as a base of said bipolar transistor, of said semiconductor region is sandwiched between a predetermined portion of said emitter and a predetermined portion of said collector, with other portions of said emitter and collector than said predetermined portions thereof overlapping portions of said diffused regions; and (e) forming, at one end of said current channel, a drain for said field effect transistor having said first conductivity type.

Claim 6

A process for manufacturing an integrated semiconductor device including a bipolar transistor and a field effect transistor formed in a single common semiconductor wafer comprising a semiconductor region having a first conductivity type and a low impurity concentration, which process comprises the steps of: (a) forming, on one surface of said semiconductor region, a double-mask layer made from a first film and a second film superposed on said first film and having apertures formed through said double-mask layer; (b) diffusing an impurity element of a predetermined first conductivity type into said semiconductor region through said apertures to form diffused regions have said first conductivity type and a predetermined impurity concentration; (c) selectively etching said first film through said apertures and widening at least partially said apertures on said first film, thereby obtaining new apertures on said first film; (d) diffusing an impurity element of a second conductivity type opposite to said first conducivity type into said semiconductor region through said new apertures to form an emitter of said bipolar transistor, a collector of said bipolar transistor, and a gate of said field effect transistor merged into said collector, and controlling the diffusion in this step so that said gate, emitter and collector have a depth less than that of said diffused regions, said new apertures being formed in said step (c) so as having dimensions such that said gate surrounds a predetermined region, which is defined as a current channel of said field effect transistor, of said semiconductor region at a predetermined portion of said gate, with a portion of the gate excluding said predetermined portion thereof overlapping a portion of at least one of said diffused regions, and that another predetermined region, which is defined as a base of said bipolar transistor, of said semiconductor region is sandwiched between a predetermined portion of said emitter and a predetermined portion of said collector, with other portions of said emitter and collector than said predetermined portions thereof overlapping portions of said diffused regions; and (e) forming, at one end of said current channel, a drain for said field effect transistor having said first conductivity type.

Claim 7

The process according to claim 4 wherein said step (e) comprises the steps of unmasking said one end portion of said current channel to be exposed, and thereafter diffusing an impurity element of said first conductivity type into said unmasked one end portion to form another diffused portion serving as said drain.

Claim 8

The process according to claim 4 wherein the impurity element used in said step (b) has said second conductivity type, and the diffusion in said step (b) is controlled so that said diffused region has a low impurity concentration.

Claim 9

The process according to claim 4 wherein the impurity element used in said step (b) has said first conductivity type, and the diffusion in said step (b) is controlled so that said diffused regions have a high impurity concentration.

Claim 10

A process for manufacturing a semiconductor device having at least three self-aligning semiconductor regions, said process comprising the steps of: (a) forming on a surface of a semiconductor body a double-masking member comprising a lower mask and an upper mask having different constituents from each other; (b) selectively removing portions of said double-masking member to form apertures therethrough and forming first semiconductor regions having a first impurity in said semiconductor body through said apertures; (c) selectively removing portions of said lower mask and then removing said upper mask at the portions where the lower mask has been removed, thereby enlarging said apertures; (d) doping a second impurity through said enlarged apertures; (e) selectively removing portions of said double-masking member to leave at least a portion thereof; (f) forming second semiconductor regions to be shallower than said first semiconductor regions so that each of said second semiconductor regions at least partially overlaps the corresponding member of said first semiconductor regions and forming a masking layer which is thicker than but integral with said lower mask of said remaining double-masking member; (g) removing said remaining double-masking member and reducing the thickness of said masking layer to expose the semiconductor body at the portion of said remaining double-masking member; and (h) forming at least one third semiconductor region of a third impurity at said exposed semiconductor body.

Claim 11

A process for manufacturing a semiconductor device having at least three self-aligning semiconductor regions, said process comprising the steps of: (a) forming on a surface of a semiconductor body a double-masking member comprising a lower mask and an upper mask having different constituents from each other; (b) selectively removing portions of said double-masking member to form apertures therethrough and forming first semiconductor regions having a first impurity in said semiconductor body through said apertures; (c) selectively removing portions of said lower mask and then removing said upper mask at the portions where the lower mask has been removed, thereby enlarging said apertures; (d) doping a second impurity through said enlarged apertures; (e) selectively removing portions of said double-masking member to leave at least a portion thereof; (f) forming second semiconductor regions to be shallower than said first semiconductor regions so that each of said second semiconductor regions at least partially overlaps the corresponding member of said first semiconductor regions and forming a masking layer which is thicker than but integral with said lower mask of said remaining double-masking member; (g) removing said remaining double-masking member and reducing the thickness of said masking layer to expose the semiconductor body at the portion of said remaining double-masking member; and (h) forming at least one third semiconductor region of a third impurity at said exposed semiconductor body.

Claim 12

The process according to claim 8 wherein said first impurity has a conductivity type opposite to that of said second impurity and said third impurity and said semiconductor body have the same conductivity type as that of said first impurity, and said first, second and third regions have a low resistivity.

Claim 13

The process according to claim 8 wherein said lower mask is made of SiO 2 , and forming said second semiconductor regions to be shallower in step (f) by driving-in said second impurity while heating said semiconductor body in an oxidizing atmosphere, and the forming of the masking layer is carried out by forming an SiO 2 layer throughout the exposed surface produced after the double-masking member has been selectively removed and at the same time after the second impurity is driven-in due to said heating.

Claim 14

The process according to claim 8, 9 or 10 further comprising, between step (e) and step (f), the additional step of selectively removing said a portion left by the step (e).