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US4419762A
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Asynchronous status register
Assignee: Unisys Corp
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Filing: 1982-02-08
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Granted: 1983-12-06
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Expires: 2002-02-08
Abstract
Abstract A register circuit which is used to asynchronously monitor any data or logical function (or functions) and be able to retain the status of the monitoring until the register is interrogated whereupon the register is automatically reset and able to receive or monitor another status signal.
Inventors
- 👤 Dieter G. Paul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
94 words
An asynchronous status register comprising, first bistable means connected to receive input signals, second bistable means connected to receive signals from said first bistable means, third bistable means connected to receive signals from said second bistable means, means connecting said second bistable means to said first bistable means to selectively reset said first bistable means, means connecting said third bistable means to said second bistable means to selectively change the state of said second bistable means, and control means for supplying signals to said second and third bistable means to selectively permit operation thereof.
Claim 2
Dependent Claim
94 words
An asynchronous status register comprising, first bistable means connected to receive input signals, second bistable means connected to receive signals from said first bistable means, third bistable means connected to receive signals from said second bistable means, means connecting said second bistable means to said first bistable means to selectively reset said first bistable means, means connecting said third bistable means to said second bistable means to selectively change the state of said second bistable means, and control means for supplying signals to said second and third bistable means to selectively permit operation thereof.
Claim 3
Dependent Claim
24 words
The asynchronous status register recited in claim 1 wherein, said first, second and third bistable means comprises first, second and third flip-flop means, respectively.
Claim 4
Dependent Claim
18 words
The asynchronous status register recited in claim 2 wherein, said first and third flip-flop means comprise D-type flip-flops.
Claim 5
Dependent Claim
17 words
The asynchronous status register recited in claim 2, wherein, said second flip-flop means comprises a J-K flip-flop.
Claim 6
Dependent Claim
22 words
The asynchronous status register recited in claim 1 including, gate means connected between said second bistable means and said first bistable means.
Claim 7
Dependent Claim
21 words
The asynchronous status register recited in claim 1 including, output means connected to receive output signals from said third bistable means.
Claim 8
Dependent Claim
21 words
The asynchronous status register recited in claim 1 including, signal means connected to receive output signals from said second bistable means.
Claim 9
Dependent Claim
29 words
The asynchronous status register recited in in claim 7, wherein, said signal means includes driver means for producing a signal representative of the condition of said second bistable means.
Claim 10
Dependent Claim
31 words
The asynchronous status register recited in claim 6 wherein, said output means includes output gate means for selectively producing an output signal representative of the state of said third bistable means.
Claim 11
Dependent Claim
18 words
The asynchronous status register recited in claim 9, wherein, said output gate means includes a tri-state gating device.
Claim 12
Dependent Claim
23 words
The asynchronous status register recited in claim 1 including, input means connected to selectively supply an input signal to said first bistable means.
Claim 13
Dependent Claim
29 words
The asynchronous status register recited in claim 11 wherein, said input means comprises a logic circuit and said input signal is representative of the status of said logic circuit.
Claim 14
Dependent Claim
26 words
The asynchronous status register recited in claim 6 wherein, said output means includes bus line means connected to selectively receive signals from said third bistable means.
Claim 15
Dependent Claim
14 words
The register recited in claim 5 wherein, said gate means comprises an AND gate.
Claim 16
Dependent Claim
20 words
The register recited in claim 14 wherein, said AND gate is connected to receive signals from said second bistable means.
Claim 17
Dependent Claim
26 words
The register recited in claim 1 wherein, said control means provides a clear signal for selectively resetting each of said first, second and third bistable means.
Claim 18
Dependent Claim
33 words
The register recited in claim 12 wherein, said input means supplies a clock signal to said first bistable means to selectively operate said first bistable means as a function of said input signal.
Claim 19
Dependent Claim
27 words
The register recited in claim 4 wherein, the K input terminal of said second flip-flop means is connected to the output terminal of said third flip-flop means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |