Transformerless bipolar converter

Claim 2

Apparatus for converting a two-level input signal to a three-level output signal such that one of the two levels of the input signal is coded as the center level of the three levels and the other of the two levels of the input signal is coded alternately as one or the other of the outer levels of the output signal, the apparatus comprising; means for alternately charging and discharging a capacitor through a load resistor responsive to successive occurrences of the other of the two levels of the input signal; and means for inhibiting the charging or discharging of the capacitor through the load resistor responsive to the occurrence of the one of the two levels of the input signals, the alternately charging and discharging means providing one or the other of the outer levels of the three level output signal across the load resistor, the inhibiting means providing the center level of the three level output signal across the load resistor.

Claim 3

An arrangement for converting a two-level data input signal to a three-level output signal such that one of the two levels of the input signal is coded as a center level of the three levels and the other of the two levels of the input signal is coded alternately as one or the other of the outer levels of the output signal comprising, logic circuit means with an input and first and second outputs, the logic circuit means separating the two levels of the input signal onto distinct outputs, inhibit circuit means with two inputs and an output, the inputs of the inhibit circuit means being respectively connected to the first and second outputs of the logic circuit means; and a resistor means connected between the output of the inhibit circuit means and a ground, the first output of the logic circuit means providing a signal corresponding to the one level of the input signal for preventing the inhibit circuit means from functioning, and resulting in the center level of the three level output signal being provided across the resistor means and the second output of the logic circuit means providing a signal corresponding to the other level of the input signal for allowing the inhibit circuit means to function, resulting in one or the other of the outer levels of the three level output signal being provided across the resistor means.

Claim 4

An arrangement for converting a two-level data input signal to a three-level output signal such that one of the two levels of the input signal is coded as a center level of the three levels and the other of the two levels of the input signal is coded alternately as one or the other of the outer levels of the output signal comprising, logic circuit means with an input and first and second outputs, the logic circuit means separating the two levels of the input signal onto distinct outputs, inhibit circuit means with two inputs and an output, the inputs of the inhibit circuit means being respectively connected to the first and second outputs of the logic circuit means; and a resistor means connected between the output of the inhibit circuit means and a ground, the first output of the logic circuit means providing a signal corresponding to the one level of the input signal for preventing the inhibit circuit means from functioning, and resulting in the center level of the three level output signal being provided across the resistor means and the second output of the logic circuit means providing a signal corresponding to the other level of the input signal for allowing the inhibit circuit means to function, resulting in one or the other of the outer levels of the three level output signal being provided across the resistor means.

Claim 5

The arrangement of claim 2 in which said inhibit circuit means comprises inhibitor means with a pair of inputs and an output, and a capacitor, one end of the capacitor being connected to the output of the inhibitor means and the other end of the capacitor being connected to the resistor means, the inhibitor means inhibiting the charging and discharging of the capacitor responsive to the occurrence of the one of the two levels of the input signal and the inhibitor means permitting the capacitor to be alternately charged and discharged through the resistor means responsive to successive occurrences of the other of the two levels of the input signal.

Claim 6

The arrangement of claim 2 in which said logic circuit means comprises first and second flip-flop means with inputs and outputs, an input to the first flip-flop means receiving said two-level input signal, means for connecting a first output of the first flip-flop to control the inhibit circuit means, exclusive-OR means having two inputs and an output, the output of the exclusive-OR means connected to an input of the second flip-flop means as a memory means, the output of the exclusive-OR means connected to the input of the inhibit circuit means, and means for connecting a second output of the first flip-flop and an output of the second flip-flop to the inputs of the exclusive-OR means.

Claim 7

The arrangement of claim 2 in which the inhibit circuit means comprises; an inverter with two inputs and an output, the inputs of the inverter connected to the outputs of the logic circuit means; and a capacitor, one side of which is connected to the output of the inverter; the other side of which is connected to the resistor means.

Claim 8

The arrangement of claim 3 in which the inhibitor means is an inverter.

Claim 9

Apparatus for converting a two-level input signal to a three-level output signal such that one of the two levels of the input signal is coded as a center level of the three levels and the other of the two levels of the input signal is coded alternately as one or the other outer level of the output signal, the apparatus comprising, an inhibit means with an input and an output, the inhibit means responsive to the other of two levels of the input signal and inhibited by the one of the two levels, of the input signals, and a capacitor and a load resistor connected in series to the output of the inhibit means and a ground, the inhibit means preventing the capacitor from charging or discharging through the load resistor responsive to the occurrence of the one of the two levels of the input signal, resulting in the center level of the three level output signal being provided across the load resistor, the inhibit means allowing the capacitor to be alternately charged and discharged through the load resistor responsive to successive occurrences of the other of the two levels of the input signal, resulting in the outer levels of the three level output signal being provided across the load resistor.

Claim 10

Apparatus for converting a two-level input signal to a three-level output signal such that one of the two levels of the input signal is coded as a center level of the three levels and the other of the two levels of the input signal is coded alternately as one or the other outer level of the output signal, the apparatus comprising, an inhibit means with an input and an output, the inhibit means responsive to the other of two levels of the input signal and inhibited by the one of the two levels, of the input signals, and a capacitor and a load resistor connected in series to the output of the inhibit means and a ground, the inhibit means preventing the capacitor from charging or discharging through the load resistor responsive to the occurrence of the one of the two levels of the input signal, resulting in the center level of the three level output signal being provided across the load resistor, the inhibit means allowing the capacitor to be alternately charged and discharged through the load resistor responsive to successive occurrences of the other of the two levels of the input signal, resulting in the outer levels of the three level output signal being provided across the load resistor.