Apparatus and method for digitally generating a modified duobinary signal

Claim 3

The process of claim 1 wherein the method of digitally transforming further consists of: a first step of digitally inverting the state of only the first level of a present digit of said binary pulse train and only when the state of the immediately preceding digit is of said first level to obtain a binary waveform of partially altered characteristics; and a second step of digitally inverting the state of only the first level of the present digit of the binary waveform of partially altered characteristics and only when the state of the immediately preceding digit is of said first level to obtain an altered binary pulse train wherein each bit is correlated with the second preceding bit of said binary pulse train.

Claim 4

The process of claim 2 wherein the method of digitally converting further consists of: delaying by two digits the altered binary pulse train and the complement of the altered binary pulse train to obtain delayed altered and complementary delayed altered pulse trains; comparing the altered binary pulse train with the complement of the delayed altered pulse train to obtain a first compared binary pulse train having a second level when the altered and complementary delayed altered pulse trains are both of a first binary level and of a first level for all other combinations; comparing the complement of the altered binary pulse train with the delayed altered pulse train to obtain a second compared binary pulse train having a second level when the complementary altered and the delayed altered are both of the first binary level and of a first level for all other combinations; and combining the first and second compared binary pulse trains to obtain a pseudo-ternary digital waveform having extreme levels representing a first signal level of said binary pulse train and a center level representing the second level thereof.

Claim 5

Apparatus for digitally generating a modified duobinary signal from a binary pulse train having first and second levels which comprises: timing means having a clock pulse rate equal to the bit rate of said binary pulse train; means for digitally transforming the binary pulse train into an altered binary pulse train at said clock rate wherein each bit is correlated with the second preceding bit; and means for converting the altered binary pulse train into a pseudo-ternary digital waveform having extreme levels representing a first signal level of said binary pulse train and a center level representing a second signal level thereof, the correlating sequence of signal levels establishing a fixed-pattern relationship between pairs of extreme signal levels of the pseudo-ternary waveform.

Claim 6

Apparatus for digitally generating a modified duobinary signal from a binary pulse train having first and second levels which comprises: timing means having a clock pulse rate equal to the bit rate of said binary pulse train; means for digitally transforming the binary pulse train into an altered binary pulse train at said clock rate wherein each bit is correlated with the second preceding bit; and means for converting the altered binary pulse train into a pseudo-ternary digital waveform having extreme levels representing a first signal level of said binary pulse train and a center level representing a second signal level thereof, the correlating sequence of signal levels establishing a fixed-pattern relationship between pairs of extreme signal levels of the pseudo-ternary waveform.

Claim 7

The apparatus of claim 4 wherein said digital transforming means further comprises: a first logic means arranged to change an input binary pulse train into a partially altered binary pulse train by inverting first-level signals only when the preceding digit is a first-level signal; and a second logic means arranged to change the partially altered binary pulse train by inverting first level signals of the partially altered binary pulse train only when the preceding digit of the partially altered pulse train is a first level signal, said second logic means providing at outputs thereof the altered waveform and the complement of said altered waveform.

Claim 8

The apparatus of claim 5 wherein said means for converting further comprises: means for delaying both the altered binary pulse train and the complement thereof by two digits; a first gating means responsive to the input signals of the altered binary pulse train and to the delayed complement thereof to provide a first gated binary output signal wherein a second level output signal is obtained whenever the two input signals are both of a first signal level, and a first signal level output is obtained for all other combinations of said input signals; a second gating means responsive to input signals of the complement of the altered binary pulse train and to the delayed altered binary pulse train to provide a second gated binary output signal wherein a second level output signal is obtained whenever the two input signals are both of a first signal level, and a first signal level output is obtained for all other combinations of said binary input signals; and means for comparing said first and second compared binary output signals, said comparing means providing a digital output wherein the center level is obtained whenever said compared signals are both of a first level, and extreme level signals are obtained for all the combinations of said compared signals.

Claim 9

The apparatus of claim 6 wherein said means for transforming further comprises: a first J-K flip-flop having both the J and K inputs arranged for connection to receive the binary pulse train and providing a Q-output; and a second J-K flip-flop having both the J and K inputs arranged for connection to the Q-output of said first flip-flop, said second flip-flop providing the altered binary pulse train at the Q-output thereof and the complement of the altered binary pulse train at the Q-output thereof.

Claim 10

The apparatus for claim 7 wherein said means for delaying further comprises: a third J-K flip-flop having the J-input connected to the Q-output of said second flip-flop and the K-input connected to the Q-output of said second flip-flop, said second flip-flop providing Q and Q-output signals; and a fourth J-K flip-flop having the J-input connected to the Q-output of said third flip-flop, the K-input connected to the Q-output of said third flip-flop, said fourth flip-flop providing the altered binary pulse train delayed by two digits at the Q-output, and the complement of the altered binary pulse train delayed by two digits at the Q-output.

Claim 11

The apparatus of claim 8 wherein said first and second gating means are NAND-gates.

Claim 12

The apparatus of claim 9 wherein said comparing means further comprises: a first transistor means having an input connected to the output of said first gating means, said first transistor means providing a lower extreme level output only when said first gating means provides a first level input to said first transistor means and said second gating means provides a second level output; and a second transistor means having an input connected to the output of said second gating means, said second transistor means providing an extreme upper-level output only when said second gating means provides a first level input to said second transistor means and said first gating means provides a second level input to said first transistor means.