Patent US4418293A successfully refreshed from Google Patents.
US4418293A
Expired / Lapsed
US
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High performance dynamic sense amplifier with multiple column outputs
Assignee: Texas Instruments Inc
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Filing: 1980-10-22
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Granted: 1983-11-29
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Expires: 2000-10-22
Abstract
Abstract A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.
Inventors
- 👤 Joseph C. McAlexander, III
- 👤 Lionel S. White, Jr.
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:33
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/403; G11C11/404; G11C11/4076; G11C11/4093; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
292 words
A semiconductor memory device of the type having an array of rows and columns of memory cells at a face of a semiconductor body with each column split into two column line halves and having sense amplifiers connected to pairs of sense nodes at ends of each pair of column line halves, the columns being arranged in M groups of N columns where M and N are integers and M is greater than N, comprising: a pair of cross-coupled driver transistors in each sense amplifier, and at least one grounding transistor, each of the transistors having a current path and a control electrode, means connecting the current path of each one of the driver transistors separately between one of the sense nodes and a grounding node and connecting the current path of the grounding transistor between the grounding node and reference potential, means for precharging the sense nodes to a voltage level prior to an active operating cycle, means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, means for applying a clock voltage to turn on said at least one grounding transistor at a first time subsequent to the said given time in the beginning of an active operating cycle, a plurality of N pairs of column output lines running parallel to said rows of cells, each pair including a data line and a data line, and selectively-activated coupling means connecting each of said column output lines separately to one of said column line halves in each group, and column addressing means connected to said coupling means to activate said coupling means in one group at a time after said given time in an active operating cycle.
Claim 2
Dependent Claim
292 words
A semiconductor memory device of the type having an array of rows and columns of memory cells at a face of a semiconductor body with each column split into two column line halves and having sense amplifiers connected to pairs of sense nodes at ends of each pair of column line halves, the columns being arranged in M groups of N columns where M and N are integers and M is greater than N, comprising: a pair of cross-coupled driver transistors in each sense amplifier, and at least one grounding transistor, each of the transistors having a current path and a control electrode, means connecting the current path of each one of the driver transistors separately between one of the sense nodes and a grounding node and connecting the current path of the grounding transistor between the grounding node and reference potential, means for precharging the sense nodes to a voltage level prior to an active operating cycle, means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, means for applying a clock voltage to turn on said at least one grounding transistor at a first time subsequent to the said given time in the beginning of an active operating cycle, a plurality of N pairs of column output lines running parallel to said rows of cells, each pair including a data line and a data line, and selectively-activated coupling means connecting each of said column output lines separately to one of said column line halves in each group, and column addressing means connected to said coupling means to activate said coupling means in one group at a time after said given time in an active operating cycle.
Claim 3
Dependent Claim
23 words
A device according to claim 1 wherein the memory cells are of the dynamic type each having one transistor and one storage capacitor.
Claim 4
Dependent Claim
36 words
A device according to claim 2 wherein all of said transistors are insulated gate field effect transistors, the current path of each of the transistors being a source-to-drain path and the control electrode being a gate.
Claim 5
Dependent Claim
29 words
A device according to claim 1 wherein the means for precharging comprises a pair of precharge transistors having current paths separately connecting a precharge node to said sense nodes.
Claim 6
Dependent Claim
43 words
A device according to claim 4 wherein the precharge node varies in voltage from said voltage level to an intermediate level then to reference potential during an active operating cycle then slowly rises back to said voltage level after an active operating cycle.
Claim 7
Dependent Claim
12 words
A device according to claim 1 wherein the integer N is four.
Claim 8
Dependent Claim
29 words
A device according to claim 1 wherein the selectively-activated coupling means are field-effect transistors and all such transistors for a group of column lines are activated at one time.
Claim 9
Dependent Claim
276 words
A semiconductor memory device having an array of rows and columns of memory cells at a face of a semiconductor body with row lines connected to the rows of cells and column lines connected to the columns of cells, and having sense amplifiers connected to column lines, the column lines being in M groups of N columns per group, where M and N are integers and M is greater than N, comprising: a pair of cross-coupled driver transistors and a pair of sense nodes in each sense amplifier, each transistor having a current path and a control electrode, means connecting the current path of each of the driver transistors separately between a sense node and a common grounding node, grounding means for connecting the common grounding nodes to reference potential, means for coupling sense nodes of the sense amplifiers to column lines, a plurality of N pairs of column output lines extending along the array parallel to the row lines, each pair including a data line and a data line, and selectively-activated coupling means connecting the column lines to the column output lines, means for precharging the sense nodes to a voltage level prior to an active operating cycle, row addressing means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, means for activating said grounding means at a first time subsequent to said given time in the beginning of an active operating cycle, and column addressing means for activating said coupling means for a group of N column lines at a time after said given time in an active operating cycle.
Claim 10
Dependent Claim
276 words
A semiconductor memory device having an array of rows and columns of memory cells at a face of a semiconductor body with row lines connected to the rows of cells and column lines connected to the columns of cells, and having sense amplifiers connected to column lines, the column lines being in M groups of N columns per group, where M and N are integers and M is greater than N, comprising: a pair of cross-coupled driver transistors and a pair of sense nodes in each sense amplifier, each transistor having a current path and a control electrode, means connecting the current path of each of the driver transistors separately between a sense node and a common grounding node, grounding means for connecting the common grounding nodes to reference potential, means for coupling sense nodes of the sense amplifiers to column lines, a plurality of N pairs of column output lines extending along the array parallel to the row lines, each pair including a data line and a data line, and selectively-activated coupling means connecting the column lines to the column output lines, means for precharging the sense nodes to a voltage level prior to an active operating cycle, row addressing means for addressing a selected row of the memory cells in the array at a given time in the beginning of said operating cycle, means for activating said grounding means at a first time subsequent to said given time in the beginning of an active operating cycle, and column addressing means for activating said coupling means for a group of N column lines at a time after said given time in an active operating cycle.
Claim 11
Dependent Claim
20 words
A device according to claim 8 wherein said transistors, said grounding means, and said coupling means are insulated-gate field-effect transistors.
Claim 12
Dependent Claim
12 words
A device according to claim 9 wherein the integer N is four.
Claim 13
Dependent Claim
20 words
A device according to claim 9 wherein the memory cells are dynamic cells each having one transistor and one capacitor.
Claim 14
Dependent Claim
28 words
A device according to claim 11 wherein the coupling means of only one of the M groups are all activated at one time by the column addressing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-28 | 1987-05-30 | 1987-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-28 | 1991-05-30 | 1991-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-28 | 1995-05-30 | 1995-11-29 | $7700.00 | Window Closed / Lapsed |