Zero tracking circuit for electronic weighing scale

Claim 2

In a weighing device including a weight transducer for developing an analog electrical signal proportional to an applied weight, converter means for converting the analog weight signal to a corresponding digital output signal, said converter means including resettable counter means for accumulating a count as a function of said weight signal, and a digital display for displaying said output count, the improvement comprising: a zero tracking circuit including decoder means responsive to an output of said counter means for detecting a low magnitude counter output that is characteristic of drift and means responsive to said decoder means for resetting said counter means, said resetting means including means responsive to said decoder means for generating reset pulses identifying low magnitude counter outputs characteristic of drift, accumulator means for accumulating said reset pulses and means responsive to a predetermined number of reset pulses in said accumulator means for resetting said counter means.

Claim 3

A circuit for digitally displaying the magnitude of an input analog signal comprising a source of clock pulses, means for generating a timing signal proportional to the instantaneous magnitude of the input signal, resettable up-down counter means responsive to the timing signals for successively upcounting and downcounting clock pulses and means responsive to said timing signal for latching an output count of said counter means; decoder means for monitoring the output count at a time whereat said count is proportional to the input signal magnitude; means for displaying said output count at said time and means responsive to said decoder means for resetting said counter means when said output count at said time has a value that is characteristic of drift, said resetting means including means responsive to said decoder means for generating reset pulses identifying a low magnitude counter output characteristic of drift, accumulator means for accumulating said reset pulses and means responsive to a predetermined number of reset pulses in said accumulator means for resetting said counter means.

Claim 4

A circuit for digitally displaying the magnitude of an input analog signal comprising a source of clock pulses, means for generating a timing signal proportional to the instantaneous magnitude of the input signal, resettable up-down counter means responsive to the timing signals for successively upcounting and downcounting clock pulses and means responsive to said timing signal for latching an output count of said counter means; decoder means for monitoring the output count at a time whereat said count is proportional to the input signal magnitude; means for displaying said output count at said time and means responsive to said decoder means for resetting said counter means when said output count at said time has a value that is characteristic of drift, said resetting means including means responsive to said decoder means for generating reset pulses identifying a low magnitude counter output characteristic of drift, accumulator means for accumulating said reset pulses and means responsive to a predetermined number of reset pulses in said accumulator means for resetting said counter means.

Claim 5

A circuit for digitally displaying the magnitude of an input analog signal, comprising a source of clock pulses; dual slope integrating analog to digital converter means responsive to said input signal, said converter means including a dual slope integrator means, up-down counter means, means for controlling said counter means to successively upcount and downcount clock pulses; means responsive to said integrating means to latch an output count of said counter means at a display time whereat said output count is proportional to input signal magnitude; latch means for storing digital signals developed by said counter means at said display time; means for displaying contents of said latch means; said circuit further comprising decoder means for monitoring the count at said display time and means responsive to an output of said decoder means for resetting said counter means when said count at said display time has a magnitude characteristic of drift, said resetting means including means responsive to said decoder means for generating reset pulses identifying low magnitude counter outputs characteristic of drift, accumulator means for accumulating said reset pulses and means responsive to a predetermined number of reset pulses in said accumulator means for resetting said counter means.

Claim 6

A circuit for digitally displaying the magnitude of an input analog signal, comprising a source of clock pulses; dual slope integrating analog to digital converter means responsive to said input signal, said converter means including a dual slope integrator means, up-down counter means, means for controlling said counter means to successively upcount and downcount clock pulses; means responsive to said integrating means to latch an output count of said counter means at a display time whereat said output count is proportional to input signal magnitude; latch means for storing digital signals developed by said counter means at said display time; means for displaying contents of said latch means; said circuit further comprising decoder means for monitoring the count at said display time and means responsive to an output of said decoder means for resetting said counter means when said count at said display time has a magnitude characteristic of drift, said resetting means including means responsive to said decoder means for generating reset pulses identifying low magnitude counter outputs characteristic of drift, accumulator means for accumulating said reset pulses and means responsive to a predetermined number of reset pulses in said accumulator means for resetting said counter means.

Claim 7

The circuit defined in any one of claims 1, 2, or 3, further including manually operated tare means for resetting said counter means.

Claim 8

The circuit defined in any one of claims 1, 2, or 3, further including means for isolating the counter means and display means and responsive to said decoder means for zeroing said display means independently of said counter means during resetting of said counter means by said resetting means to prevent a count corresponding to drift from being displayed by said display means.

Claim 9

In a weighing scale of a type comprising a transducer for developing an analog signal proportional to magnitude of an applied weight to be displayed in a display, a source of clock pulses; analog to digital converter means for converting the analog weight responsive signal to a corresponding digital signal and means for displaying said digital signal; said converter means including means for sampling the analog input signal means for generating timing pulses having interpulse spacing proportional to analog signal magnitude, resettable counter means, means for controlling said counter means to successively upcount and downcount said clock pulses, and means responsive to said timing signals for latching an output count in said counter means at a display time whereat said count is proportional to the magnitude of an input analog voltage sample, and means for resetting said counter means: a zero tracking method comprising the steps of monitoring the output of said counter means at the display times, generating a reset pulse when the monitored count has a magnitude corresponding to drift, accumulating said reset pulses and resetting said counter means upon accumulation of a predetermined number of said reset pulses.

Claim 10

In a weighing scale of a type comprising a transducer for developing an analog signal proportional to magnitude of an applied weight to be displayed in a display, a source of clock pulses; analog to digital converter means for converting the analog weight responsive signal to a corresponding digital signal and means for displaying said digital signal; said converter means including means for sampling the analog input signal means for generating timing pulses having interpulse spacing proportional to analog signal magnitude, resettable counter means, means for controlling said counter means to successively upcount and downcount said clock pulses, and means responsive to said timing signals for latching an output count in said counter means at a display time whereat said count is proportional to the magnitude of an input analog voltage sample, and means for resetting said counter means: a zero tracking method comprising the steps of monitoring the output of said counter means at the display times, generating a reset pulse when the monitored count has a magnitude corresponding to drift, accumulating said reset pulses and resetting said counter means upon accumulation of a predetermined number of said reset pulses.

Claim 13

The method of claim 6 or 7, including the step of zeroing said display independently of said counter means during said resetting step to prevent a count corresponding to drift from being displayed by said display means.

Claim 14

A circuit fo digitally displaying the magnitude of an input analog signal comprising a source of clock pulses, means for generating a timing signal proportional to the instantaneous magnitude of the input signal, resettable up-down counter means responsive to the timing signals for successively upcounting and downcounting clock pulses and means responsive to said timing signal for latching an output count of said counter means; decoder means for monitoring the output count at a time whereat said count is proportional to the input signal magnitude; means for displaying said output count at said time and means responsive to said decoder means for resetting said counter means when said output count at said time has a value that is characteristic of drift, further including means for isolating the counter means and display means and responsive to said decoder means for zeroing said display means independently of said counter means during resetting of said counter means by said resetting means to prevent a count corresponding to drift from being displayed by said display means.

Claim 15

A circuit fo digitally displaying the magnitude of an input analog signal comprising a source of clock pulses, means for generating a timing signal proportional to the instantaneous magnitude of the input signal, resettable up-down counter means responsive to the timing signals for successively upcounting and downcounting clock pulses and means responsive to said timing signal for latching an output count of said counter means; decoder means for monitoring the output count at a time whereat said count is proportional to the input signal magnitude; means for displaying said output count at said time and means responsive to said decoder means for resetting said counter means when said output count at said time has a value that is characteristic of drift, further including means for isolating the counter means and display means and responsive to said decoder means for zeroing said display means independently of said counter means during resetting of said counter means by said resetting means to prevent a count corresponding to drift from being displayed by said display means.