Static semiconductor memory device

Claim 1

A static semiconductor memory device, operatively connected to receive column selection signals, comprising: a plurality of memory cells arranged in a matrix having columns and rows, each of said plurality of memory cells comprising two driving transistors connected in intersection; a plurality of word lines connected to said plurality of memory cells and arranged in the row direction; a plurality of bit lines connected to said plurality of memory cells and arranged in the column direction, each bit line connectable to receive a current for reading information stored in or for writing information to be stored in said plurality of memory cells; a common current source; a plurality of bit selection circuits operatively connected to said common current source and operatively connected to respective ones of said columns of said matrix, each of said plurality of bit selection circuits operatively connected to receive a corresponding one of said column selection signals having a first reference potential, when the corresponding column is selected, and to supply a current from said common current source to said corresponding selected column; a plurality of bit driver circuits respectively, operatively connected to said columns of said matrix, each of said plurality of bit driver circuits connected to cause said column selection signal to have said first reference potential when the corresponding column is selected; a discharge current source; and means forming a plurality of discharge paths, each of said discharge paths being connected between a respective one of said plurality of bit selection circuits and said discharge current source, for functioning so that when a column in said matrix is switched from a selected state to a nonselected state, the potential of the corresponding column selection signal is changed to a second potential through said discharge path.