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US4417264A Expired / Lapsed US ⏱️ 0.0 years remaining

Electrically alterable, nonvolatile floating gate memory device

Assignee: RCA Corp
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Filing: 1983-03-07
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Granted: 1983-11-22
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Expires: 2003-03-07
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Abstract

Abstract A novel, nonvolatile floating gate memory structure is described wherein the floating gate is substantially shielded from the substrate by the control gate. The control gate is provided with a pair of apertures, through which portions of the floating gate extends. One aperture serves as means for "writing" and "erasing" while the other aperture serves as means for "reading".

Inventors

  • 👤 Rodney L. Angle

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 15:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 215 words
In a floating gate memory device of the type including a body of semiconductor material of a first conductivity type having first and second doped regions of a second conductivity type formed in the semiconductor body at the surface thereof, the first and second doped regions spaced one from the other to define a channel region therebetween in the semiconductor body for supporting current flow between the doped regions, a first conductive layer insulated from the body of the semiconductor material, a second conductive layer positioned over both the channel region and the first conductive layer and insulated therefrom, the first conductive layer having a first aperture therein into which the second conductive layer extends, the improvement comprising: a first portion of the channel region, adjacent the first doped region having a pair of depletion type regions embedded in the semiconductor body at the surface thereof and spaced one from the other to define a first channel portion therebetween; a second aperture in the first layer of polysilicon, aligned with the first channel portion, into which a portion of the second conductive layer extends; a second channel portion adjacent the second doped region and occupying the remainder of the channel region; and a third conductive layer positioned over and insulated from the second channel portion.
Claim 2
Dependent Claim 215 words
In a floating gate memory device of the type including a body of semiconductor material of a first conductivity type having first and second doped regions of a second conductivity type formed in the semiconductor body at the surface thereof, the first and second doped regions spaced one from the other to define a channel region therebetween in the semiconductor body for supporting current flow between the doped regions, a first conductive layer insulated from the body of the semiconductor material, a second conductive layer positioned over both the channel region and the first conductive layer and insulated therefrom, the first conductive layer having a first aperture therein into which the second conductive layer extends, the improvement comprising: a first portion of the channel region, adjacent the first doped region having a pair of depletion type regions embedded in the semiconductor body at the surface thereof and spaced one from the other to define a first channel portion therebetween; a second aperture in the first layer of polysilicon, aligned with the first channel portion, into which a portion of the second conductive layer extends; a second channel portion adjacent the second doped region and occupying the remainder of the channel region; and a third conductive layer positioned over and insulated from the second channel portion.
Claim 3
Dependent Claim 35 words
The floating gate memory device of claim 1, wherein: the first and second doped regions are source and drain regions, respectively; and one of the pair of depletion regions is adjacent to the source region.
Claim 4
Dependent Claim 34 words
The floating gate memory device of claim 2, wherein: the first conductive layer is a control gate; the second conductive layer is a floating gate; and the third conductive layer is a word line.
Claim 5
Dependent Claim 69 words
The floating gate memory device of claim 3, wherein: the control gate and the word line are each insulated from the surface of the channel region by a layer of silicon oxide of about 1,000 angstroms; and the portion of the floating gate that extends into the second aperture in the control gate is insulated from the channel region by a layer of silicon oxide of about 1,000 angstroms.
Claim 6
Dependent Claim 32 words
The floating gate memory device of claim 4, wherein: the body of semiconductor material is a well region of the first conductivity type formed in a substrate of the second conductivity type.
Claim 7
Dependent Claim 37 words
The floating gate memory device of claim 5 wherein: the material of the first, second and third conductive layers are selected from the group consisting of doped polycrystalline silicon, a refractory metal and a refractory metal silicide.

References Cited (Backward Citations)

US3500142A Cited
US3825946A Cited
US4099196A Cited
US4203158A Cited
US4203158B1 Cited
US4328565A Cited
US4336603A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-11-21 1987-05-23 1987-11-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-11-21 1991-05-23 1991-11-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-11-21 1995-05-23 1995-11-22 $7700.00 Window Closed / Lapsed

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