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Patent US4415994A successfully refreshed from Google Patents.
US4415994A
Expired / Lapsed
US
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Random access memory arrangements
Assignee: Sony Corp
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Filing: 1981-09-14
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Granted: 1983-11-15
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Expires: 2001-09-14
Abstract
Abstract A random access memory arrangement for reading data out of and into a random access memory asynchronously, for example, to effect time base correction of a digital television signal, comprises a random access memory having common read and write data terminals, an input circuit for supplying input data to said read and write data terminals for writing in the random access memory, a first output latch circuit connected to the read and write data terminals, a second output latch circuit connected to the first latch circuit, and means for supplying control signals to enable the random access memory to write the input data therein at given addresses in synchronism with write pulses of a write pulse signal, to enable the random access memory to read output data from given addresses therein in synchronism with read pulses of a read pulse signal, the read pulse signal being asynchronous with the write pulse signal, to control the first output latch circuit to hold and to supply to the second output latch circuit data supplied to the first latch circuit immediately prior to each write pulse, and to pass therethrough to the second latch circuit data supplied to the first latch circuit at all other times, and to control the second latch circuit to hold the data supplied to it by the first latch circuit immediately prior to the beginning of each read pulse until the beginning of the next succeeding read pulse and to supply the data so held to an output of the arrangement.
Inventors
- 👤 John G. S. Ive
- 👤 Alan C. Thirlwall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:47
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/16; G11; G11C; G11C7/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
301 words
A random access memory arrangement comprising: a random access memory having common read and write data terminals; means for supplying input data to said read and write data terminals for writing in said random access memory; a first output latch circuit connected to said read and write data terminals; a second output latch circuit connected to said first output latch circuit and having an output; means responsive to a write pulse signal having write pulses, for supplying control signals to said random access memory to enable said random access memory to write said input data therein at given addresses in synchronism with said write pulses of said write pulse signal; means responsive to a read pulse signal having read pulses, for supplying control signals to said random access memory to enable said random access memory to read output data from given addresses therein in synchronism with said read pulses of said read pulse signal, said read pulse signal being asynchronous with said write pulse signal; means responsive to said write pulse signal for supplying signals to control said first output latch circuit to hold and to supply to said second output latch circuit data supplied to said first output latch circuit immediately prior to each said write pulse, and to pass therethrough to said second output latch circuit data supplied to said first output latch circuit at all other times; and means for supplying said read pulse signal to said second output latch circuit for causing the latter to hold the data supplied to said second output latch circuit by said first output latch circuit immediately prior to the beginning of each said read pulse until the beginning of the next succeeding said read pulse and to supply the data so held to said output of said second output latch circuit.
Claim 2
Dependent Claim
301 words
A random access memory arrangement comprising: a random access memory having common read and write data terminals; means for supplying input data to said read and write data terminals for writing in said random access memory; a first output latch circuit connected to said read and write data terminals; a second output latch circuit connected to said first output latch circuit and having an output; means responsive to a write pulse signal having write pulses, for supplying control signals to said random access memory to enable said random access memory to write said input data therein at given addresses in synchronism with said write pulses of said write pulse signal; means responsive to a read pulse signal having read pulses, for supplying control signals to said random access memory to enable said random access memory to read output data from given addresses therein in synchronism with said read pulses of said read pulse signal, said read pulse signal being asynchronous with said write pulse signal; means responsive to said write pulse signal for supplying signals to control said first output latch circuit to hold and to supply to said second output latch circuit data supplied to said first output latch circuit immediately prior to each said write pulse, and to pass therethrough to said second output latch circuit data supplied to said first output latch circuit at all other times; and means for supplying said read pulse signal to said second output latch circuit for causing the latter to hold the data supplied to said second output latch circuit by said first output latch circuit immediately prior to the beginning of each said read pulse until the beginning of the next succeeding said read pulse and to supply the data so held to said output of said second output latch circuit.
Claim 3
Dependent Claim
55 words
An arrangement according to claim 1, wherein said means for supplying input data comprises an input latch circuit connected to said read and write data terminals of said random access memory, said input latch circuit receiving said write pulse signal for controlling the supplying of said input data to said read and write data terminals.
Claim 4
Dependent Claim
59 words
An arrangement according to claim 2, wherein said means responsive to said write pulse signal for supplying signals to control said first output latch circuit comprises means to derive a read inhibit pulse signal in synchronism with said write pulses of said write pulse signal, said read inhibit pulse signal being supplied to control said first output latch circuit.
Claim 5
Dependent Claim
75 words
An arrangement according to claim 1, wherein said means responsive to said write pulse signal for supplying control signals to said random access memory includes a write address generator and a write address latch circuit, for supplying write addresses to said random access memory from said write address generator by way of said write address latch circuit, said write address generator and said write address latch circuit being synchronously controlled by said write pulse signal.
Claim 6
Dependent Claim
75 words
An arrangement according to claim 4, wherein said means responsive to said read pulse signal for supplying control signals to said random access memory includes a read address generator and a read address latch circuit, for supplying read addresses to said random access memory from said read addresses generator by way of said read address latch circuit, said read address generator and said read address latch circuit being synchronously controlled by said read pulse signal.
Claim 7
Dependent Claim
17 words
An arrangement according to claim 1, wherein said first output latch circuit is a transparent latch circuit.
Claim 8
Dependent Claim
17 words
An arrangement according to claim 1, wherein said second output latch circuit is an edge-triggered latch circuit.
References Cited (Backward Citations)
US3402398A
Cited
US3560940A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-14 | 1987-05-16 | 1987-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-14 | 1991-05-16 | 1991-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-14 | 1995-05-16 | 1995-11-15 | $7700.00 | Window Closed / Lapsed |