Methods of making narrow channel field effect transistors

Claim 3

The method of claim 1 further comprising the step of forming in said substrate a pair of source and drain regions of conductivity-type opposite to said selected conductivity-type at the ends of said narrow channel regions to produce a pair of low current CIS transistors.

Claim 4

The method of claim 2 wherein the steps of forming said pair of gate structures and forming said source and drain regions comprise: forming a layer of insulating material on said substrate overlying said narrow channel regions; forming a patterned layer of conductive material on said insulating material in the form of strips each overlying one of said narrow channel regions; forming a patterned layer of masking material on said layer of conductive material to define end boundaries of said pair of gate electrodes and apertures for said source and drain regions; removing at least said layer of conductive material exposed through said patterned layer of masking material; and implanting ions of opposite conductivity-type into said substrate to form said source and drain regions using said patterned layers of masking material as a mask.

Claim 5

The method of claim 2 wherein the steps of forming said pair of gate structures and forming said source and drain regions comprise: forming a gate insulator layer overlying said narrow channel regions; forming a layer of semiconductive material on said gate insulator layer; forming a layer of silicon nitride on said layer of semiconductive material; selectively removing portions of said silicon nitride and said semiconductive material to form separate strips thereof overlying said narrow channel regions; growing a relatively thick silicon oxide layer on said substrate in the region between said strips; selectively removing said nitride layer; selectively removing portions of at least said semiconductive material to complete the formation of said pair of gate structures and to define a mask pattern for source and drain regions in said substrate; and doping simultaneously said semiconductive material and said source and drain regions of said substrate.

Claim 6

The method of claim 1, wherein the step of forming said pair of separate conductor-insulator gate structures each overlying one of said narrow channel regions comprises the steps of: forming a layer of insulating material on said substrate overlying said narrow channel regions; forming a layer of semiconductive material on said layer of insulating material; forming a diffusion mask element on said semiconductive material to define an intermediate gate structure overlying both of said narrow channel regions; laterally diffusing a selected dopant into said layer of semiconductive material underneath said diffusion mask barrier to form doped regions in said semiconductive material overlying said narrow channel regions in said substrate and separated from each other by a central undoped region of said semiconductive material; selectively removing said diffusion masking element; and subjecting said semiconductive material to an etchant which preferentially etches said undoped region thereof to form a pair of narrow doped semiconductive elements overlying said narrow channel regions.