Patent US4409678A successfully refreshed from Google Patents.
US4409678A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-02-13
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Granted: 1983-10-11
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Expires: 2001-02-13
Abstract
Abstract Disclosed is a semiconductor memory device which comprises a sense amplifier formed on a semiconductor substrate, paired bit lines connected to the sense amplifier and memory cells connected to the bit lines wherein a predetermined bias voltage is applied to the semiconductor substrate and the reading operation is performed by amplifying by the sense amplifier a voltage difference caused between the paired bit lines due to access to the memory cells. This semiconductor memory device is characterized in that a voltage of a phase reverse to a noise transmitted to the bias voltage applied to the semiconductor substrate is applied to the semiconductor substrate through an electrostatic capacitance formed on the semiconductor substrate to cancel the noise. By virtue of this characteristic feature, influences of such noises can be eliminated in the semiconductor memory device of the present invention.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Fumio Baba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:26
CPC Classifications
G; G11; G11C; G11C7/00; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/409; G11C11/4091
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
143 words
A semiconductor memory device, operatively connected to receive a cancelling voltage, comprising: a semiconductor substrate having a predetermined bias voltage applied thereto; a sense amplifier; a pair of bit lines operatively connected to said sense amplifier; memory cells formed on said semiconductor substrate and operatively connected to said pair of bit lines; and a capacitance formed on said semiconductor substrate and operatively connected to receive said cancelling voltage, wherein the predetermined bias voltage is applied to the semiconductor substrate and a reading operation is performed by amplifying through said sense amplifier a voltage difference caused between said pair of bit lines due to access to one of said memory cells, and wherein said cancelling voltage of a phase reverse to that of a noise disturbing said predetermined bias voltage applied to said semiconductor substrate is applied to said semiconductor substrate through said capacitance.
Claim 2
Dependent Claim
143 words
A semiconductor memory device, operatively connected to receive a cancelling voltage, comprising: a semiconductor substrate having a predetermined bias voltage applied thereto; a sense amplifier; a pair of bit lines operatively connected to said sense amplifier; memory cells formed on said semiconductor substrate and operatively connected to said pair of bit lines; and a capacitance formed on said semiconductor substrate and operatively connected to receive said cancelling voltage, wherein the predetermined bias voltage is applied to the semiconductor substrate and a reading operation is performed by amplifying through said sense amplifier a voltage difference caused between said pair of bit lines due to access to one of said memory cells, and wherein said cancelling voltage of a phase reverse to that of a noise disturbing said predetermined bias voltage applied to said semiconductor substrate is applied to said semiconductor substrate through said capacitance.
Claim 3
Dependent Claim
66 words
A semiconductor memory device as set forth in claim 1, wherein said cancelling voltage of a phase reverse to that of the noise is a voltage cancelling a variation of the voltage of the semiconductor substrate due to the variation of the voltage of said pair of bit lines which is caused when said voltage difference is amplified by said sense amplifier during the reading operation.
Claim 4
Dependent Claim
148 words
A semiconductor memory device, operatively connectable to receive a word line signal, a bit line signal and a latch enable signal, comprising: a substrate; a memory cell formed on said substrate; a word line formed on said substrate, operatively connected to said memory cell and operatively connectable to receive the word line signal; a bit line operatively connected to said memory cell and operatively connectable to receive the bit line signal; a noise cancelling capacitor formed on said substrate; a bulk bias generator, operatively connected to said substrate, for generating a bulk bias voltage signal; and a bulk noise compensator, operatively connected to said noise cancelling capacitor and operatively connectable to receive the latch enable signal, for generating a cancelling signal having a phase reversed with respect to the phase of the bit line signal, the cancelling signal cancelling out noise imparted to the bulk bias voltage signal.
Claim 5
Dependent Claim
148 words
A semiconductor memory device, operatively connectable to receive a word line signal, a bit line signal and a latch enable signal, comprising: a substrate; a memory cell formed on said substrate; a word line formed on said substrate, operatively connected to said memory cell and operatively connectable to receive the word line signal; a bit line operatively connected to said memory cell and operatively connectable to receive the bit line signal; a noise cancelling capacitor formed on said substrate; a bulk bias generator, operatively connected to said substrate, for generating a bulk bias voltage signal; and a bulk noise compensator, operatively connected to said noise cancelling capacitor and operatively connectable to receive the latch enable signal, for generating a cancelling signal having a phase reversed with respect to the phase of the bit line signal, the cancelling signal cancelling out noise imparted to the bulk bias voltage signal.
Claim 6
Dependent Claim
66 words
A semiconductor memory device as recited in claim 3, wherein said bulk noise compensator comprises: a delay circuit, operatively connectable to receive the latch enable signal, for generating a delay signal; a bootstrap circuit, operatively connected to said delay circuit, for generating bootstrap signals; and an output transistor circuit, operatively connected to said bootstrap circuit and to said noise cancelling capacitor, for generating the cancelling signal.
Claim 7
Dependent Claim
73 words
A semiconductor memory device as set forth in claim 3, further comprising: means, operatively connected to said word line, for generating the word line signal; a latch enable circuit, operatively connected to said means for generating the word line signal and said bulk noise compensator, for generating the latch enable signal; and a sense amplifier, operatively connected to said latch enable circuit and to said bit line, for generating the bit line signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |