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US4409675A
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Address gate for memories to protect stored data, and to simplify memory testing, and method of use thereof
Assignee: National Semiconductor Corp
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Filing: 1980-12-22
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Granted: 1983-10-11
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Expires: 2000-12-22
Abstract
Abstract An address gate for a random access memory includes a pair of emitter-coupled and collector-coupled transistors, and another transistor emitter-coupled to the pair of transistors. Complimentary outputs are read at the coupled emitters of the pair of transistors and the collector of the other transistor respectively, there being an input signal applied to the base of one of the pair of transistors, and a control signal applied to the base of the other of the pair of transistors, which overrides the operation of one of the pair of transistors when the control signal is in its high state.
Inventors
- 👤 Jonathan J. Stinehelfer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:25
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G11; G11C; G11C8/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
72 words
A method of addressing a random access memory comprising in order the steps of: addressing the memory at a particular address; addressing the memory at an address other than said particular address; (i) addressing the memory at said particular address; (ii) addressing the memory at an address not previously addressed and other than said particular address, and repeating said steps (i) and (ii) until all addresses in the memory have been addressed.
Claim 2
Independent Claim
72 words
A method of addressing a random access memory comprising in order the steps of: addressing the memory at a particular address; addressing the memory at an address other than said particular address; (i) addressing the memory at said particular address; (ii) addressing the memory at an address not previously addressed and other than said particular address, and repeating said steps (i) and (ii) until all addresses in the memory have been addressed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |