Normally-on enhancement mode MOSFET with negative threshold gating

Claim 1

A Normally-On enhancement mode MOSFET having a gate threshold voltage for nonconduction comprising: a semiconductor substrate of a first conductivity type, said substrate being very lightly doped such that it has a relatively very high resistivity of at least 300 ohm centimeters, a heavily doped source region and a heavily doped drain region provided at a surface of said substrate, said regions being of a second conductivity type whereby source and drain junctions are provided, each of said junctions having a depletion region associated therewith due to the built-in potential of the junction, said depletion regions extending substantially into said substrate due to the very light doping of said substrate, and an insulated gate electrode coupled to said surface of said substrate adjacent said source and drain regions, said source and drain regions being separated by a substrate channel of a length not greater than about one micron whereby said depletion regions associated with said junctions overlap in said channel from source region to drain region due to the substantial extension of said depletion regions into said substrate, the electric field associated with the overlapped depletion regions being of sufficient magnitude to create an inversion layer of said second conductivity type in said channel extending from source region to drain region, said surface inversion layer providing a conduction path through said channel as between said source and drain regions such that said MOSFET is normally in the conduction mode without application of said threshold gate voltage for nonconduction to said gate electrode.