Altimeter code converter

Claim 1

An altitude code converter that has input a parallel signal being Gray coded for altitude information and that outputs a binary serial word acceptable to a computer comprising: an input data interface connected for receiving the altitude information coded parallel signal and connected for outputting an adjusted parallel signal having a plurality of adjusted bit signals, said input data interface having a plurality of adjusting circuits equal in number to the number of bit signals of the parallel signal, each of said adjusting circuits having buffer amplifying means therein; a conversion device connected for receiving the adjusted parallel signal output from said input data interface and connected for outputting a binary serial signal, said conversion device including a code conversion circuit for converting the adjusted parallel signal to a binary parallel signal representing actual altitude in binary notation, said code conversion circuit being memory means having a lookup table therein, said memory means addressed by a plurality of said adjusted bit signals and outputting a 16 bit binary parallel signal having a decimal equivalent value of an altitude input to said altitude code converter in Gray code, and a memory select circuit connected for selecting read-only memories to be addressed; a data conversion circuit for receiving the binary parallel signal and outputting a binary serial signal having a predetermined bit length and having a parity bit inserted therein, said data conversion circuit including at least one parallel-to-serial shift register for outputting a 32 bit serial signal without parity and a parity generator connected for inserting a parity bit into said 32 bit serial signal; and a data control circuit for outputting timing signals to said code conversion circuit and said data conversion circuit, said data control circuit including a pair of counters connected for having input initializing signals from said condition present circuit and a strobe signal from said computer and outputting a plurality of counting signals to a timing signal generator comprising a plurality of gates and inverters, said timing signal generator outputting a clock signal, a data gating signal during a data shift period, a data enable signal, a parity signal, a chip select signal, and a load signal; an output data interface connected for receiving the binary serial signal and for outputting said binary serial computer word; a condition preset circuit connected for initializing said conversion device; means for powering, said means for powering including a circuit connected for providing a plurality of fixed voltages to said code converter and a circuit connected for indicating external power failure to said conversion device.