Serial gray-to-binary translator with clock transition timing

Claim 2

A serial gray to binary translator for decoding the digital words in a data signal having digit durations of a predetermined interval, said translator comprising: a source of digit timing pulses which provides at least one voltage transition during each of said digit durations and which also provides the complements of said digit timing pulses; a source of word timing pulses which provides at least a portion of a pulse during a first digit in each of said digital words; means responsive to said voltage transition for providing synchronized digital pulses which indicate the logical zeroes and ones of said data signal; means responsive to the complement of said digit timing pulses and to said word timing pulses for providing during a first digit a synchronized word pulse; and pulse processing means responsive to said synchronized digital pulses and to said synchronized word pulses for providing at its output a decoding of said data signal.

Claim 3

A translator as defined in claim 1 wherein said pulse processing means comprises: first and second decoding means, each operating in accordance with a decoding algorithm and each having a control input which disables decoding when activated; and means for coupling said synchronized word pulse to the control input of each of said decoding means.

Claim 4

A digital translator for converting Gray code signals to corresponding binary code signals in accordance with a conversion algorithm defined by first and seconD equations comprising: a source of an indicating signal having pulses associated with corresponding digits of the Gray code signals, said indicating signal designating the one of said equations which defines the conversion procedure for each of the Gray code digits; a source of timing pulses, each of said timing pulses having at least one voltage transition during each of the Gray code digits; means for developing the complement of the timing pulses, each pulse in said complement having at least one voltage transition occurring during each pulse of said indicating signal; means responsive to a voltage transition in the complement of the timing pulses for sampling the indicating signal; means responsive to a voltage transition in the timing pulses, for sampling the Gray code signals, a Gray digit being sampled subsequent to the sampling of an associated pulse of the indicating signal; first and second decoding means, the operation of each of said decoding means being defined respectively by said equations; and conversion control means responsive to said sampled indicating signals for controlling the operation of said decoding means, said conversion control means enabling one of said decoding means and disabling the other of said decoding means; whereby a voltage transition of the complement of said timing pulses enables the decoding means predictively to anticipate the desired conversion procedure for the corresponding digit to be translated upon the occurrence of a voltage transition of the associated timing pulse.

Claim 5

A digital translator for converting Gray code signals to corresponding binary code signals in accordance with a conversion algorithm defined by first and seconD equations comprising: a source of an indicating signal having pulses associated with corresponding digits of the Gray code signals, said indicating signal designating the one of said equations which defines the conversion procedure for each of the Gray code digits; a source of timing pulses, each of said timing pulses having at least one voltage transition during each of the Gray code digits; means for developing the complement of the timing pulses, each pulse in said complement having at least one voltage transition occurring during each pulse of said indicating signal; means responsive to a voltage transition in the complement of the timing pulses for sampling the indicating signal; means responsive to a voltage transition in the timing pulses, for sampling the Gray code signals, a Gray digit being sampled subsequent to the sampling of an associated pulse of the indicating signal; first and second decoding means, the operation of each of said decoding means being defined respectively by said equations; and conversion control means responsive to said sampled indicating signals for controlling the operation of said decoding means, said conversion control means enabling one of said decoding means and disabling the other of said decoding means; whereby a voltage transition of the complement of said timing pulses enables the decoding means predictively to anticipate the desired conversion procedure for the corresponding digit to be translated upon the occurrence of a voltage transition of the associated timing pulse.

Claim 6

A digital translator as claimed in claim 3 wherein a first one of said decoding means comprises means for storing converted binary digits and means, responsive to said sampled Gray code digits and to a preceding one of said stored binary digits, for producing a subsequent binary digit, said subsequent digit being identical to said preceding digit whenever the corresponding Gray code digit is a logical zero and said subsequent digit being the complement of said preceding binary digit whenever the corresponding Gray code digit is a logical one.

Claim 7

A digital translator as claimed in claim 3 wherein said means for sampling the indicating signal and said means for sampling the Gray code signals each comprises first, second, third, and fourth gating means, the output of each of said gating means being connected to inputs of preceding and succeeding ones of said gating means, sampling signals being applied at the inputs of said second and third gating means and signals to be sampled being applied at the inputs of said first and fourth gating means, sampled signals appearing at the outputs of said second and third gating means.

Claim 8

A serial digital translator for converting gray coded words having a plurality of digital bits to corresponding binary code in accordance with a conversion algorithm defined by first and second equations comprising: first and second decoding means, each respectively operating in accordance with the procedures defined by said first and second equations; a source of digit timing signals, each signal corresponding to a digital bit and having first and second voltage levels during each digital bit time; a source of signals for providing predetermined logical states during predetermined bits of said digital word, said logical states indicating which of said decoding means is to be utilized means responsive to a change to said first voltage level and to the logical state of said source of signals, for enabling one of said decoding means and for disabling the other of said decoding means; and means responsive to a change to said second voltage level of said digital timing pulses for coupling the corresponding digital bit in said digital word to each of said decoding means.

Claim 9

A serial digital translator for converting gray coded words having a plurality of digital bits to corresponding binary code in accordance with a conversion algorithm defined by first and second equations comprising: first and second decoding means, each respectively operating in accordance with the procedures defined by said first and second equations; a source of digit timing signals, each signal corresponding to a digital bit and having first and second voltage levels during each digital bit time; a source of signals for providing predetermined logical states during predetermined bits of said digital word, said logical states indicating which of said decoding means is to be utilized means responsive to a change to said first voltage level and to the logical state of said source of signals, for enabling one of said decoding means and for disabling the other of said decoding means; and means responsive to a change to said second voltage level of said digital timing pulses for coupling the corresponding digital bit in said digital word to each of said decoding means.