Patent US4409496A successfully refreshed from Google Patents.
US4409496A
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MOS Device including a substrate bias generating circuit
Assignee: Fujitsu Ltd
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Filing: 1980-06-04
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Granted: 1983-10-11
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Expires: 2000-06-04
Abstract
Abstract An MOS device including a substrate bias generating circuit, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; an internal circuit operated by the first and second internal clock signals; a pumping circuit driver for generating third and fourth internal clock signals in synchronization with the first and second internal clock signals and; a pumping circuit operated by the third and fourth internal clock signals. In this device, when the substrate potential (V BB ) is relatively high, currents flow from the substrate to the pumping circuit.
Inventors
- 👤 Fumio Baba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11C11/4063; G11C11/407; G11C11/4074; H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
163 words
An MOS device including a substrate bias circuit for controlling the potential on a substrate containing said MOS device, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; a circuit internal to said MOS device connected to said clock generator and operated by said first and second internal clock signals; a pumping circuit driver, connected to said clock generator, for receiving said first and second internal clock signals and generating third and fourth internal clock signals which are in synchronization with said first and second internal clock signals and are in opposite phase with each other; and a pumping circuit connected to said pumping circuit driver and said substrate and driven by said third and fourth internal clock signals, for generating a potential for biasing said substrate when said pumping circuit effectuates a pumping operation, said pumping circuit effecting said pumping operation when the potential on said substrate is higher than a predetermined value.
Claim 2
Dependent Claim
163 words
An MOS device including a substrate bias circuit for controlling the potential on a substrate containing said MOS device, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; a circuit internal to said MOS device connected to said clock generator and operated by said first and second internal clock signals; a pumping circuit driver, connected to said clock generator, for receiving said first and second internal clock signals and generating third and fourth internal clock signals which are in synchronization with said first and second internal clock signals and are in opposite phase with each other; and a pumping circuit connected to said pumping circuit driver and said substrate and driven by said third and fourth internal clock signals, for generating a potential for biasing said substrate when said pumping circuit effectuates a pumping operation, said pumping circuit effecting said pumping operation when the potential on said substrate is higher than a predetermined value.
Claim 3
Dependent Claim
21 words
A device as set forth in claim 1, wherein said internal circuit is a memory cell array including a sense amplifier.
Claim 4
Dependent Claim
16 words
A device as set forth in claim 1, wherein said internal circuit is a decoder circuit.
Claim 5
Dependent Claim
125 words
A device as set forth in claim 1, wherein said pumping circuit comprises: a transistor having first, second and third terminals, said first and second terminals connected to said substrate of said MOS device; a diode operatively connected to said first and third terminals of said transistor; a capacitor having a first terminal operatively connected to said diode and the third terminal of said transistor to form a node and having a second terminal, said transistor, said diode and said capacitor serving as a pump for absorbing positive charges in said substrate; and a plurality of switching transistors operatively connected to said pumping circuit driver and said second terminal of said capacitor for receiving said third and fourth internal clock signals and actuating said pump.
Claim 6
Dependent Claim
27 words
A device as set forth in claim 4, wherein said pump operates only when the potential at said node is less than the potential on said substrate.
Claim 7
Dependent Claim
37 words
A device as set forth in claim 1, 2, 3 or 4, wherein said pumping circuit operates only when said first internal clock signal is at a high potential with respect to said second internal clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |