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US4408337A
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Television base signal and test signal generator
Assignee: Thales SA
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Filing: 1981-02-20
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Granted: 1983-10-04
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Expires: 2001-02-20
Abstract
Abstract A television base signal and test signal generator comprises a first memory for storing n eight-bit words (n being a positive whole number) located by a pair of indices (i, j) and a second memory for storing t four-bit words (t being a positive whole number) located by an index k. A first counter and a second counter supply respectively the index i associated with the word to be read in the first memory and the index k associated with the word to be read in the second memory. The index j associated with the word to be read in the first memory corresponds to the value of the four-bit word supplied by the second memory. The two memories are programmed so that at all times the eight bits of the word read in the first memory define entirely the desired base signals and test signals.
Inventors
- 👤 Luc Pham van Cang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:51
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
187 words
A generator of television base signals and test signals comprising: a first memory with p memory zones each having q memory cells (p and q being positive whole numbers), each cell storing an assembly of bits defining entirely, for a quantum of time T 0 , the amplitude of base signals and test signals able to be generated, said first memory having a first and a second address input and an output; a second memory with t memory cells (t being a positive whole number), each cell storing a binary number which is the address of a memory zone of the first memory, this second memory having an address input and having an output coupled to the first address input of the first memory; a first counter having an output coupled to the address input of the second memory for reading successively its t memory cells; a second counter having an output coupled to the second address input of the first memory for reading, at a frequency 1/T 0 , the memoory cells of the memory zone associated with the binary number delivered by the second memory.
Claim 2
Dependent Claim
187 words
A generator of television base signals and test signals comprising: a first memory with p memory zones each having q memory cells (p and q being positive whole numbers), each cell storing an assembly of bits defining entirely, for a quantum of time T 0 , the amplitude of base signals and test signals able to be generated, said first memory having a first and a second address input and an output; a second memory with t memory cells (t being a positive whole number), each cell storing a binary number which is the address of a memory zone of the first memory, this second memory having an address input and having an output coupled to the first address input of the first memory; a first counter having an output coupled to the address input of the second memory for reading successively its t memory cells; a second counter having an output coupled to the second address input of the first memory for reading, at a frequency 1/T 0 , the memoory cells of the memory zone associated with the binary number delivered by the second memory.
Claim 3
Dependent Claim
93 words
The television base signal and test signal generator as claimed in claim 1 wherein the first counter is a counter from 0 to t-1 at a frequency 1/nTo (n being a positive whole number), and wherein the second counter is a counter from 0 to q-1 at a frequency 1/T o , the counting duration from 0 to q-1 of the second counter and the counting duration from 0 to t-1 of the first counter being respectively equal to the duration of a television line and to the duration of a television frame.
Claim 4
Dependent Claim
72 words
The television base signal and test signal as claimed in claim 1, wherein the first and second counter have respectively a clock input, wherein the second counter has an auxiliary output coupled to the clock input of the first counter, and furthermore comprising a clock circuit coupled to the clock input of the second counter and a control device coupled to the clock circuit to synchronize this latter on an external signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-03 | 1987-04-04 | 1987-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-03 | 1991-04-04 | 1991-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-03 | 1995-04-04 | 1995-10-04 | $7700.00 | Window Closed / Lapsed |