US4326219A
Expired / Lapsed
US
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Digital error measuring circuit for shading and registration errors in television cameras
Assignee: Ampex Corp
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Filing: 1980-04-11
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Granted: 1982-04-20
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Expires: 2000-04-11
Abstract
Abstract To provide measurement of horizontal and vertical spatial errors, as well as shading errors, the active video picture is divided horizontally into 13 equal blocks, and vertically into 14 bands of checkers. During the setup mode, the signal from a selected camera is fed to an A/D converter in the video signal path, and to sync and pattern validation circuits which provide control and timing signals and an electronic test pattern signal. Horizontal error measurement is provided via a horizontal adder/memory loop whereby selected samples within the blocks of successive horizontal lines are selectively summed to provide successive pairs of summed horizontal digital data. Vertical error measurement is done simultaneously by a vertical adder/memory circuit whereby selected adjacent samples of alternate checkers are selectively delayed and added, to provide successive pairs of summed vertical digital data. During a read cycle, the horizontal and vertical pairs of digital data are selectively subtracted to inherently cancel the effects of existing shading errors, blooming, crosstalk, etc., and the difference signals are D/A converted. The horizontal and vertical transition and zero crossing information is established, and the transitions information are compared with the electronic test pattern signal to derive the digital horizontal and vertical spatial error data for storage in a microprocessor memory. Shading error data are provided from the vertical adder/memory circuit and also are stored in the microprocessor memory. The stored error data are subsequently retrieved and used to provide spatial and shading correction during the camera operating mode.
Inventors
- 👤 Karl H. Griesshaber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:21
CPC Classifications
H; H04; H04N; H04N23/00; H04N23/10; H04N23/13; H04N23/15; H04N23/80; H04N23/81
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
152 words
A circuit for measuring H and V spatial and shading errors existing between a video test signal generated by a pickup tube of a television camera head and an electronic test pattern signal of perfect geometry, comprising the combination of; means for receiving the video test pattern signal and for digitizing therefrom digital data A and data B corresponding to summations of selected digital samples of the video test signal which contain shading error effects; memory means coupled to the means for receiving and digitizing for selectively storing the digital data A and data B; means coupled to the memory means for selectively subtracting data A and data B to provide digital difference data without the shading error effects; and means coupled to the means for subtracting and to the electronic test pattern signal for comparing the digital difference data with the electronic test pattern signal to provide the spatial error information.
Claim 2
Dependent Claim
152 words
A circuit for measuring H and V spatial and shading errors existing between a video test signal generated by a pickup tube of a television camera head and an electronic test pattern signal of perfect geometry, comprising the combination of; means for receiving the video test pattern signal and for digitizing therefrom digital data A and data B corresponding to summations of selected digital samples of the video test signal which contain shading error effects; memory means coupled to the means for receiving and digitizing for selectively storing the digital data A and data B; means coupled to the memory means for selectively subtracting data A and data B to provide digital difference data without the shading error effects; and means coupled to the means for subtracting and to the electronic test pattern signal for comparing the digital difference data with the electronic test pattern signal to provide the spatial error information.
Claim 3
Dependent Claim
38 words
The circuit of claim 1 including; shading error measurement means coupled to the memory means for receiving the data A and data B and for providing an average value thereof corresponding to the white and black shading errors.
Claim 4
Dependent Claim
45 words
The circuit of claim 1 wherein the means for comparing includes; filter/comparator means for generating initial transition error data corresponding to the digital difference data; microprocessor/memory means coupled to the filter/comparator means and to the electronic test pattern signal to provide the spatial error information.
Claim 5
Dependent Claim
39 words
The circuit of claim 3 wherein; the memory means includes H adder/memory means and V adder/memory means coupled to the means for digitizing for providing respective H data A and data B, and V data A and data B.
Claim 6
Dependent Claim
42 words
The circuit of claim 4 wherein; the subtraction means digitally subtracts the H data B from the H data A, and the V data B from the V data A, to provide H difference data A-B and V difference data A-B respectively.
Claim 7
Dependent Claim
32 words
The circuit of claim 5 wherein; the H adder/memory means sums selected samples from pairs of successive scans of the video test signal to provide the H data A and data B.
Claim 8
Dependent Claim
165 words
The circuit of claim 6 wherein the pickup tube generates a video active picture area corresponding to an active area of the test pattern, wherein; the active picture area and the test pattern is divided into a selected plurality of blocks in the horizontal direction, each block including a plurality of alternate white/black checkers, and into a plurality of checker bands in the vertical direction, each band including rows of the alternate white/black checkers; the H adder/memory means sums selected samples from two successions of scan lines within a block and retains the pair of summations as the H data A and H data B respectively in separate memories therein; and the V adder/memory means adds two pairs of selected samples from white checkers within a block to provide V data A, and adds two pairs of selected samples from black checkers within the same block to provide V data B, and retains the V data A and V data B in separate memories therein.
Claim 9
Dependent Claim
60 words
The circuit of claim 7 further including; shading error measurement means coupled to the V adder/memory means for receiving the V data A and V data B prior to storage in the memories, and for providing an average of selected lines of samples thereof within a block of the peak white and black video levels corresponding to the shading errors.
Claim 10
Dependent Claim
29 words
The circuit of claim 7 further including; pattern validation means coupled to the video test signal for providing a validation strobe indicative of valid data generation within selected blocks.
Claim 11
Dependent Claim
105 words
The circuit of claim 7 wherein; the H adder/memory means includes three H memories and sums samples within a block from a first succession of scans along a checker band and stores the summation as H data A in the first H memory, and also sums samples within the same block from a second succession of scans along the same checker band and stores the summation as H data B in the third H memory; and wherein the H data A and H data B are read out from respective memories for application to the subtraction means upon completion of the second succession of scans.
Claim 12
Dependent Claim
132 words
The circuit of claim 7 wherein; the V adder/memory means includes two V memories and respective delays operating simultaneously with the H adder/memory means, and adds the sum of adjacent center samples from a first white checker with the sum of adjacent center samples from a second white checker and stores the addition as V data A in the first V memory, and also adds the sum of adjacent center samples from a first black checker with the sum of adjacent samples from a second black checker and stores the addition as V data B in the second V memory; and wherein the V data A and V data B are read out from respective memories for application to the subtraction means upon completion of the H data A/B read out process.
Claim 13
Dependent Claim
64 words
The circuit of claim 7 wherein the filter/comparator means further includes; interpolation filter means coupled to the subtractor means for providing and establishing the precise transitions of the difference data A-B corresponding to the checker transitions and comparator/counter means coupled to the interpolation filter means for providing a reference zero crossing and for generating an initial transition error for application to the microprocessor/memory means.
Claim 14
Dependent Claim
49 words
The circuit of claim 12 wherein multiple camera head units are being setup, including; multiplexer means for selecting a camera head unit in response to a camera select command; and filter means for preventing the generation of aliasing components coupled between the multiplexer means and the means for digitizing.
Claim 15
Dependent Claim
56 words
The circuit of claim 13 further including; control means responsive to the video test signal for generating video signal-related clock and timing signals; and memory control means coupled to the control means and to the pattern validation means for generating timing controls and addresses for the sample summing processes of the H and V adder/memory means.
Claim 16
Dependent Claim
167 words
A measurement circuit for measuring spatial and shading errors existing between an electronic test pattern of perfect geometry and a video test signal generated by the pickup tubes of a television camera system which includes multiple camera head units and a microprocessor control with memory, comprising the combination of; H and V memory means for storing selected data A and B of respective sums of H and V digital samples of the video test signal, which data A and B contain shading error effects; means for selectively subtracting the data A and B of the H digital samples, and of the V digital samples to generate respective H and V difference data in time-shared selection which has no shading error effects; and means including the microprocessor control with memory for selectively comparing the H and V difference data with the electronic test pattern to determine the respective H and V error data corresponding to the errors existing between the pickup tube scans and the electronic test pattern.
Claim 17
Dependent Claim
167 words
A measurement circuit for measuring spatial and shading errors existing between an electronic test pattern of perfect geometry and a video test signal generated by the pickup tubes of a television camera system which includes multiple camera head units and a microprocessor control with memory, comprising the combination of; H and V memory means for storing selected data A and B of respective sums of H and V digital samples of the video test signal, which data A and B contain shading error effects; means for selectively subtracting the data A and B of the H digital samples, and of the V digital samples to generate respective H and V difference data in time-shared selection which has no shading error effects; and means including the microprocessor control with memory for selectively comparing the H and V difference data with the electronic test pattern to determine the respective H and V error data corresponding to the errors existing between the pickup tube scans and the electronic test pattern.
Claim 18
Dependent Claim
146 words
The circuit of claim 15 further including A/D converter means coupled to the video test signal to provide the H and V digital samples corresponding thereto; H and V adder means coupled to the A/D converter and integral with respective H and V memory means for selectively summing and storing the H data A and data B, and V data A and data B; said subtractor means being selectively coupled to the H adder and memory means, and to the V adder and memory means; D/A converter means coupled to the subtractor means to generate H and V analog difference signals corresponding to the H and V difference data; and means coupled to the D/A converter means for detecting and establishing the transitions in the H and V analog difference signals, wherein the microprocessor control causes the subsequent comparison thereof with the electronic test pattern transitions.
Claim 19
Dependent Claim
83 words
The circuit of claim 16 further including; timing control means coupled to the video test signal for generating clock and timing signals related to the video test signal; pattern validation means coupled to the video test signal for providing a validation strobe indicative of valid data generation; and memory control means responsive to the timing control means and to the pattern validation means for generating timing controls and addresses for the sample summing processes of the H and V adder and memory means.
Claim 20
Dependent Claim
66 words
The circuit of claim 17 further including; data switch means for selectively providing the H data A/B or the V data A/B to the subtractor means; interpolation filter means coupled to the D/A converter means to establish the transitions in the H and V difference signals; and comparator/counter means coupled to the interpolation filter means and thence operatively coupled to the memory of the microprocessor control.
References Cited (Backward Citations)
US4200934A
Cited
US4234890A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-19 | 1985-10-19 | 1986-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-19 | 1989-10-19 | 1990-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-19 | 1993-10-19 | 1994-04-20 | $7700.00 | Window Closed / Lapsed |