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US4200934A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit arrangement for correcting digital signals

Assignee: Airbus Defence and Space GmbH
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Filing: 1978-03-29
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Granted: 1980-04-29
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Expires: 1998-03-29
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Abstract

Abstract The analog output signals of a photoelectric image converter or transducer are passed through an analog-to-digital converter and then corrected to take various irregularities of the optical sensor elements of the transducer into account. A reference signal and a dark signal are subtracted from the individual image point signals. The difference is then multiplied by a factor representing the slope of the characteristic response curve of the respective optical sensor element. The so corrected signal may be used for further processing or it may be subjected to a further correction operation.

Inventors

  • 👤 Otto Hofmann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 05:39
CPC Classifications
G; G01; G01J; G01J1/00; G01J1/42; G01J1/44; G06; G06T; G06T1/00; G06T1/0007

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 431 words
An electronic circuit arrangement for correcting the output signals of a photoelectric image transducer which includes a plurality of photoelectric transducer elements, said circuit arrangement comprising analog-to-digital converter means having an input operatively connected to said image transducer and a digital signal output, a plurality of selector switch means (13, 26, 27) including first, second, and third selector switch members each having an input terminal and two alternate output terminals, a like plurality of computer means (6, 7, 8) including first, second, and third circuits each having two inputs and an output, first, second and third memory circuit means (10, 11, 12) each having at least one input and an output, and electronic switching control means (5, 25) operatively connected to said circuit arrangement, said first selector switch member (13) being connected with its input terminal to said digital signal output (4) of said analog-to-digital converter means and with one of its outputs to one input of said first computing circuit (6), said first memory circuit means (10) being connected to the other output terminal of said first selector switch means and to the other input terminal of said first computing circuit which forms a first difference signal U i -U B , said second selector switch member (26) being connected with its input terminal to the output of said first computing circuit to receive said first difference signal with one of its output terminals to the second computing circuit (7) said second memory circuit means (11) being connected to the other output terminal of said second selector switch means and to the other input terminal of said second computing circuit which forms a second difference signal (U i -U B )-D i , said third selector switch member (27) being connected with its input to the output of said second computing circuit (7) with one of its output terminals to said third memory circuit means and with its other output terminal to said third computing circuit (17), said third memory circuit means (12) being connected with an output terminal (16) to said third computing circuit (17) which multiplies the second difference signal (U i -U B )-D i with a correction factor K i which is proportional to the slope of the characteristic curve of a respective photoelectric transducer element (3) to form real time corrected output signals U Ki for each image point signal U i of a photoelectric transducer element, wherein U B is a reference signal representative of a respective scanning period and wherein D i is a dark signal of the respective scanned photoelectric transducer element.
Claim 2
Dependent Claim 431 words
An electronic circuit arrangement for correcting the output signals of a photoelectric image transducer which includes a plurality of photoelectric transducer elements, said circuit arrangement comprising analog-to-digital converter means having an input operatively connected to said image transducer and a digital signal output, a plurality of selector switch means (13, 26, 27) including first, second, and third selector switch members each having an input terminal and two alternate output terminals, a like plurality of computer means (6, 7, 8) including first, second, and third circuits each having two inputs and an output, first, second and third memory circuit means (10, 11, 12) each having at least one input and an output, and electronic switching control means (5, 25) operatively connected to said circuit arrangement, said first selector switch member (13) being connected with its input terminal to said digital signal output (4) of said analog-to-digital converter means and with one of its outputs to one input of said first computing circuit (6), said first memory circuit means (10) being connected to the other output terminal of said first selector switch means and to the other input terminal of said first computing circuit which forms a first difference signal U i -U B , said second selector switch member (26) being connected with its input terminal to the output of said first computing circuit to receive said first difference signal with one of its output terminals to the second computing circuit (7) said second memory circuit means (11) being connected to the other output terminal of said second selector switch means and to the other input terminal of said second computing circuit which forms a second difference signal (U i -U B )-D i , said third selector switch member (27) being connected with its input to the output of said second computing circuit (7) with one of its output terminals to said third memory circuit means and with its other output terminal to said third computing circuit (17), said third memory circuit means (12) being connected with an output terminal (16) to said third computing circuit (17) which multiplies the second difference signal (U i -U B )-D i with a correction factor K i which is proportional to the slope of the characteristic curve of a respective photoelectric transducer element (3) to form real time corrected output signals U Ki for each image point signal U i of a photoelectric transducer element, wherein U B is a reference signal representative of a respective scanning period and wherein D i is a dark signal of the respective scanned photoelectric transducer element.
Claim 3
Dependent Claim 87 words
The electronic circuit arrangement of claim 1, wherein said first selector switch member (13) supplies said reference signal U B at the beginning of the respective scanning period through said first memory circuit means to form said first difference signal U i -U B in said first computing circuit, and wherein said reference signal U B is further supplied by said first memory circuit means to said first computing circuit during the respective scanning period when the first computing circuit receives the scanned signals U i .
Claim 4
Dependent Claim 55 words
The electronic circuit arrangement of claim 1, further comprising shutter means and light supply means arranged for exposing said transducer elements to light, and wherein said second memory circuit means (11) has stored therein said dark signal D i which is derived from each of said transducer elements (3) when said shutter means are closed.
Claim 5
Dependent Claim 74 words
The electronic circuit arrangement of claim 3, comprising a fourth computer circuit (9) operatively connected to said electronic switching control means (5) and to said third memory circuit means (12) for forming said correction factor K i by dividing a constant value C by partially corrected brightness signals U Hi derived from said transducer elements (3) when the shutter means pass a reference light distribution from said light supply means onto said transducer elements.
Claim 6
Dependent Claim 71 words
The electronic circuit arrangement of claim 4, wherein said third memory circuit means has storage capacity of said correction factor K i and a storage capacity for said partially corrected brightness signals U Hi , said storage capacities having storing positions arranged so that storing positions becoming available by being addressed for the retrieval of the partially corrected brightness signals U Hi are occupied by the correction factors K i .
Claim 7
Dependent Claim 43 words
The electronic circuit arrangement of claim 1, comprising further computer means (18, 19) operatively connected to said second and third computing circuits, said further computer means performing a second degree or square correction of said real time corrected output signals U Ki .
Claim 8
Dependent Claim 30 words
The electronic circuit arrangement of claim 1, further comprising shutter means for exposing said transducer elements, and wherein said electronic switching control means are operatively connected to said shutter means.
Claim 9
Dependent Claim 31 words
The electronic circuit arrangement of claim 1, further comprising shutter means and a calibration light source means operatively arranged to pass light through said shutter means onto said photoelectric transducer means.
Claim 10
Dependent Claim 26 words
The electronic circuit arrangement of claim 8, wherein said calibration light source means comprise an Ulbricht-globe, and wherein said shutter means are secured to said Ulbricht-globe.

References Cited (Backward Citations)

DE2055639A1 Cited
US3653014A Cited
US3852714A Cited
US3919473A Cited
US3972626A Cited
US4084248A Cited
US4086652A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-04-29 1983-10-29 1984-04-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-04-29 1987-10-29 1988-04-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-04-29 1991-10-29 1992-04-29 $7700.00 Window Closed / Lapsed

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