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US4408306A
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Column and row erasable EEPROM
Assignee: Motorola Solutions Inc
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Filing: 1981-09-28
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Granted: 1983-10-04
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Expires: 2001-09-28
Abstract
Abstract An EEPROM has an array of memory elements arranged by row and column which is accessed by a decoder capable of selecting all columns while enabling a single row in response to one input and selecting one column while enabling all rows in response to another input, thereby selectively erasing one entire row or column.
Inventors
- 👤 Clinton C. K. Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:47
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/32; G11C16/08; G11C16/10; G11C16/12; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
136 words
An electrically erasable programmable read only memory (EEPROM) comprising: an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array; logic means for generating, in response to a row erase mode signal, a row control signal at a first logic state and a column control signal at a second logic state; column select means for coupling, when the column control signal is at the second logic state, an erase signal to all of the columns of said array; and row decoder means for enabling, when the row control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the row of said array selected in response to a row address signal.
Claim 2
Dependent Claim
136 words
An electrically erasable programmable read only memory (EEPROM) comprising: an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array; logic means for generating, in response to a row erase mode signal, a row control signal at a first logic state and a column control signal at a second logic state; column select means for coupling, when the column control signal is at the second logic state, an erase signal to all of the columns of said array; and row decoder means for enabling, when the row control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the row of said array selected in response to a row address signal.
Claim 3
Dependent Claim
111 words
The EEPROM of claim 1 wherein the column select means comprises: a plurality of column address buffer means, each column address buffer means providing two buffered address signals, one true and one complementary, of an individual column address signal when the column control signal is at a first logic state, and providing both buffered address signals at a predetermined logic state when the column control signal is at said second logic state; and column decoder means for coupling said erase signal to all of the columns of said array in response to all of the buffered address signals of the plurality of column address means being at said predetermined logic state.
Claim 4
Dependent Claim
136 words
An electrically erasable programmable read only memory (EEPROM) comprising: an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array; logic means for generating in response to a column erase mode signal a column control signal at a first logic state and a row control signal at a second logic state; row select means for coupling, when the row control signal is at the second logic state, an erase signal to all of the rows of said array; and column decoder means for enabling, when the column control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the column of said array selected in response to a column address signal.
Claim 5
Dependent Claim
136 words
An electrically erasable programmable read only memory (EEPROM) comprising: an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array; logic means for generating in response to a column erase mode signal a column control signal at a first logic state and a row control signal at a second logic state; row select means for coupling, when the row control signal is at the second logic state, an erase signal to all of the rows of said array; and column decoder means for enabling, when the column control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the column of said array selected in response to a column address signal.
Claim 6
Dependent Claim
111 words
The EEPROM of claim 3 wherein the row select means comprises: a plurality of row address buffer means, each row address buffer means providing two buffered address signals, one true and one complementary, of an individual row address signal when the row control signal is at a first logic state, and providing both buffered address signals at a predetermined logic state when the row control signal is at said second logic state; and row decoder means for coupling said erase signal to all of the rows of said array in response to all of the buffered address signals of the plurality of row address means being at said predetermined logic state.
References Cited (Backward Citations)
US4279024A
Cited
US4172291A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-03 | 1987-04-04 | 1987-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-03 | 1991-04-04 | 1991-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-03 | 1995-04-04 | 1995-10-04 | $7700.00 | Window Closed / Lapsed |