Detecting redundant digital codewords using a variable criterion

Claim 3

The invention according to claim 1 wherein the number m of consecutive codewords checked is a variable over each of the n bit-positions of the codewords, with j m varying as a function of m.

Claim 4

The invention according to claim 1, wherein said step of checking includes checking values in each of the n bit-positions initially for a low number m of consecutive codewords, and increasing m until said count of bits having equal values in that bit-position reaches the then current j m set by the then current m, or until m reaches a given maximum M.

Claim 5

The invention according to claim 3, wherein said checking the values in said bit-positions includes counting ones and zeros, and said comparing includes comparing the ones and zeros counts against variable threshold j m such that a bit detected signal is provided if either count equals or exceeds the dictated j m for the number m of codewords then currently checked for that bit-position, and providing a codeword detected signal if bit detected signals have been provided for all n bit-positions.

Claim 8

The invention according to claim 5 further comprising determining said variable threshold j m according to the first m bits in a preset J M code having M bits.

Claim 9

The invention according to claim 6, wherein said counting and comparing include counting and comparing said m bits in said given bit-position of said codewords bit by bit against said first m bits of J M providing j m .

Claim 10

The invention according to claim 7 wherein said repeated reading includes reading the same said given bit-position for successive, and successively older, codewords.

Claim 11

The invention according to claim 8 wherein the sum of the bits in the first m bits of J M is equal to j m -1.

Claim 12

The invention according to claim 8 wherein said J M code is preset according to user choice, and affords fast codeword detection by providing said bit detected signals from less than M bits when said variable threshold j m is reached.

Claim 13

The invention according to claim 8, wherein said bit by bit counting and comparing includes: separately counting ones and zeros for said m bits in said given bit-position as selectively enabled bit by bit according to the first m bits of J M , such that a given overflow of either ones-counting or zeros-counting provides said bit detected signal.

Claim 14

The invention according to claim 11 wherein a bit value signal is provided by the output of one of said countings.

Claim 15

A digital codeword detector for detecting redundant codewords repeatedly transmitted over a digital transmission system, comprising: a first memory having a bit capacity of at least n×M bits for storing M codewords, each n bits long; means for reading from said first memory the values in a given bit-position of each of a variable number m of codewords, where m≦M; means for counting, for plural bit values, the number of said bits read in said given bit-position assuming each bit value, and comparing the counts against a variable threshold j m dependent upon m, and increasing m by reading, counting and comparing for the samd said given bit-position for successive, and successively older, codewords, until one of said counts reaches j m or until m=M, and outputting a bit value signal and a bit detected signal if said one count reaches j m ; a second memory, responsive to said means for counting and comparing and having a capacity of at least n bits, for storing said bit detected signal, and outputting a codeword detected signal if its contents reach n bits; and a third memory, responsive to said means for counting and comparing and having a capacity of at least n bits, for storing said bit value signal, and outputting a codeword value signal.

Claim 16

A digital codeword detector for detecting redundant codewords repeatedly transmitted over a digital transmission system, comprising: a first memory having a bit capacity of at least n×M bits for storing M codewords, each n bits long; means for reading from said first memory the values in a given bit-position of each of a variable number m of codewords, where m≦M; means for counting, for plural bit values, the number of said bits read in said given bit-position assuming each bit value, and comparing the counts against a variable threshold j m dependent upon m, and increasing m by reading, counting and comparing for the samd said given bit-position for successive, and successively older, codewords, until one of said counts reaches j m or until m=M, and outputting a bit value signal and a bit detected signal if said one count reaches j m ; a second memory, responsive to said means for counting and comparing and having a capacity of at least n bits, for storing said bit detected signal, and outputting a codeword detected signal if its contents reach n bits; and a third memory, responsive to said means for counting and comparing and having a capacity of at least n bits, for storing said bit value signal, and outputting a codeword value signal.

Claim 17

The invention according to claim 13 wherein said counting and comparing means comprises: a shift register having a capacity of at least M bits for holding an M-bit preset code J M whose first m bits determine j m ; a ones counter for conditionally counting the number of ones in said m codeword bit-positions as selectively enabled in bit-by-bit comparison against j m from said shift register; and a zeros counter for conditionally counting the number of zeros in said m codeword bit-positions as selectively enabled in bit-by-bit comparison against j m from said shift register.

Claim 18

The invention according to claim 14, including means for shifting the m bits of j m out of said shift register one bit at a time to each of said counters to enable or disable incrementation one way or the other of each counter in bit-by-bit response to each of said respective m codeword bits.

Claim 19

The invention according to claim 15, including means for shifting the content of said shift register out bit by bit, increasing m and altering j m , until one of said counters is incremented to a given overflow or until m=M.

Claim 20

The invention according to claim 16, wherein said counting and comparing means further includes means responsive to each of said counters to provide said bit detected signal when either counter reaches said given overflow.

Claim 21

The invention according to claim 17 wherein said bit value signal is provided by the output of one of said counters.