Multiprocessor system

Claim 1

A multiprocessing system comprising a plurality of processors and a memory unit coupled to each other through a common bus to which each processor can gain access on request for an information exchange with said memory unit or for notification to another of said processors, said memory unit comprising: a control section for granting bus access to one of said processors at a time on a priority basis and on request from said processors respectively; a plurality of storage resources, each one related to one processor and accessible by all the processors for receiving and storing messages intended for the related processor; timing means activated by a control signal received through a first bus lead for starting one memory cycle and for generation of a first end signal on a second bus lead on termination of said memory cycle; said each processor comprising: first means set by the bus access granted to said processor for loading said first bus with said control signal starting a memory cycle and holding said bus until reset by a signal received from said second bus lead; second means for generating signals representative of its own processor name; third means for loading third bus leads with signals representative of the name of a processor to which messages are intended to be notified, along with a notification signal; fourth means for receiving through said third bus leads a signal representative of the name of a notified processor and said notification signal; a comparator coupled to said second and said fourth means for comparing its own processor name with said notified processor name and for generating a notify signal when said names are equal; storing means for storing said notify signal so that the notified processor is autonomously able to recognize said notify signal in said storing means at any time, without requiring attention of the notifying processor; fifth means for the generation of a second end signal on said second bus lead concurrently with the storing of said notify signal in said storing means for resetting said first means in a notifying processor; said memory further comprising: sixth means for receiving said notification signals through one of said third bus leads and for inhibiting in response thereto the activation of a memory cycle by said control signal; said plurality of storage resources each being operative to receive messages from said procesors intended for its related processor and to store said messages therein until access by its related processor upon said recognition of the notify signal in its related processor.