Semiconductor device having reduced capacitance and method of fabrication thereof

Claim 1

An inverter formed on a substrate of semiconductor material of a first conductivity type, said substrate having a field which defines the periphery of an active region and having a channel stop region of the first conductivity type but of a higher concentration of dopant than the substrate, said channel stop region being underneath the field, said inverter comprising: a first transistor having a source region doped to a second conductivity type, a channel region of the first conductivity type, and a drain region doped to the second conductivity type, formed in the active region, said drain region coupled to a first power supply terminal; a second transistor having a source region doped to the second conductivity type, a drain region doped to the second conductivity type, and a channel region of the first conductivity type formed in the active region, said source coupled to a second power supply terminal wherein the source region of the first transistor is formed in common with the drain region of the second transistor to form an output of the inverter; a first line on the surface of the substrate a first portion of which overlaps a portion of the active region and the field, a second portion of which overlies the channel region of the first transistor to form a gate thereof, said line comprising a lower insulating layer, and an upper electrically conductive layer, said upper electrically conductive layer being physically continuous between said first and second portions and electrically connected to the drain region of the first transistor; a spacer region of the first conductivity type and of substantially the same doping concentration as the substrate formed in the active region between the channel stop region and the source and drain regions of the first and second transistors, respectively, and underneath the first portion of the first line; and a second line on the surface of the substrate comprising a lower insulating layer and an upper electrically conductive layer and overlying the channel region of the second transistor to form an input of the inverter.