Patent US4404479A successfully refreshed from Google Patents.
US4404479A
Expired / Lapsed
US
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Sample-and-hold circuit
Assignee: Victor Company of Japan Ltd
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Filing: 1981-03-26
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Granted: 1983-09-13
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Expires: 2001-03-26
Abstract
Abstract In a sample-and-hold circuit having two voltage amplifiers connected in series via a switch, which is arranged to perform on-off operations in accordance with a control signal, the noninverting input terminal of the second voltage amplifier of output side is grounded so that the switch can be used at an imaginal short point of the second voltage amplifier. As a result, a semiconductor switch having a simple construction may be used as the switch, while a switch drive circuit may also be simple. Furthermore, since great negative feedback effect can be attained during sampling mode, the sample-and-hold circuit is capable of operating with high accuracy. Additional switches may be employed for improving feedthrough characteristics, while means for preventing undesirable oscillation may be provided if necessary.
Inventors
- 👤 Kazuya Toyomaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:39
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
196 words
A sample-and-hold circuit comprising: (a) a first voltage amplifier having a noninverting input terminal connected via a first resistor to an input terminal of said sample-and-hold circuit, an inverting input terminal connected via a second resistor to ground, and an output terminal; (b) a second voltage amplifier having an inverting input terminal connected via a first switch to said output terminal of said first voltage amplifier, a noninverting input terminal connected to ground, and an output terminal connected to an output terminal of said sample-and-hold circuit; (c) a hold capacitor interposed between said inverting input terminal and said output terminal of said second voltage amplifier; (d) a third resistor interposed between said noninverting input terminal of said first voltage amplifier and said output terminal of said second voltage amplifier; (e) a second switch interposed between said inverting input terminal and said output terminal of said first voltage amplifier, and arranged to perform on-off operations in opposite manner with respect to said first switch; and (f) a third switch interposed between said noninverting input terminal of said first voltage amplifier and ground, and arranged to perform on-off operations in opposite manner with respect to said first switch.
Claim 2
Dependent Claim
196 words
A sample-and-hold circuit comprising: (a) a first voltage amplifier having a noninverting input terminal connected via a first resistor to an input terminal of said sample-and-hold circuit, an inverting input terminal connected via a second resistor to ground, and an output terminal; (b) a second voltage amplifier having an inverting input terminal connected via a first switch to said output terminal of said first voltage amplifier, a noninverting input terminal connected to ground, and an output terminal connected to an output terminal of said sample-and-hold circuit; (c) a hold capacitor interposed between said inverting input terminal and said output terminal of said second voltage amplifier; (d) a third resistor interposed between said noninverting input terminal of said first voltage amplifier and said output terminal of said second voltage amplifier; (e) a second switch interposed between said inverting input terminal and said output terminal of said first voltage amplifier, and arranged to perform on-off operations in opposite manner with respect to said first switch; and (f) a third switch interposed between said noninverting input terminal of said first voltage amplifier and ground, and arranged to perform on-off operations in opposite manner with respect to said first switch.
Claim 3
Dependent Claim
30 words
A sample-and-hold circuit as claimed in claim 1, wherein said first to third switches are junction FETs arranged to perform on-off operations in accordance with a control signal applied thereto.
Claim 4
Dependent Claim
64 words
A sample-and-hold circuit as claimed in claim 1, further comprising means for compensating for phase deviation to prevent oscillation in the sample-and-hold circuit, said means comprising a capacitor interposed between said inverting input terminal and said output terminal of said first voltage amplifier, and a resistor through which said first and second switches are connected to said output terminal of said first voltage amplifier.
Claim 5
Dependent Claim
30 words
A sample-and-hold circuit as claimed in claim 1, further comprising a capacitor connected in parallel with said third resistor so as to limit the band width of the sample-and-hold circuit.
Claim 6
Dependent Claim
69 words
A sample-and-hold circuit as claimed in claim 1, further comprising a capacitor interposed between said noninverting input terminal of said second voltage amplifier and ground, and a series circuit of a fourth switch and a resistor, which series circuit is connected in parallel with said capacitor connected to said noninverting input terminal of said second voltage amplifier, said fourth switch performs the same on-off operations as said first switch.
Claim 7
Dependent Claim
29 words
A sample-and-hold circuit as claimed in claim 5, wherein said fourth switch is a junction FET arranged to perform on-off operation in accordance with a control signal applied thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |