Patent US4403395A successfully refreshed from Google Patents.
US4403395A
Expired / Lapsed
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Monolithic integration of logic, control and high voltage interface circuitry
Assignee: Texas Instruments Inc
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Filing: 1981-11-09
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Granted: 1983-09-13
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Expires: 2001-11-09
Abstract
Abstract Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.
Inventors
- 👤 Patrick A. Curran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
107 words
A process for the monolithic integration of a semiconductor circuit having D-MOS and high performance vertical NPN components, comprising the steps of: (a) providing a monocrystalline p-type semiconductor substrate having a surface layer of isolated n-type semiconductor regions thereon; (b) forming a lightly-doped p-type D-well region in each of selected said n-type regions; (c) forming p-type regions constituting the vertical NPN base and the D-MOS gate contact; (d) then selectively forming n-type regions constituting the vertical NPN emitter and collector; and (e) controlling the dopant concentration in step (b) such that said D-MOS threshold is determined by the intersection of said emitter and said D-well dopant profiles.
Claim 2
Dependent Claim
107 words
A process for the monolithic integration of a semiconductor circuit having D-MOS and high performance vertical NPN components, comprising the steps of: (a) providing a monocrystalline p-type semiconductor substrate having a surface layer of isolated n-type semiconductor regions thereon; (b) forming a lightly-doped p-type D-well region in each of selected said n-type regions; (c) forming p-type regions constituting the vertical NPN base and the D-MOS gate contact; (d) then selectively forming n-type regions constituting the vertical NPN emitter and collector; and (e) controlling the dopant concentration in step (b) such that said D-MOS threshold is determined by the intersection of said emitter and said D-well dopant profiles.
Claim 3
Dependent Claim
73 words
A process as in claim 1 wherein the vertical NPN collector contact, and the D-MOS source and drain are formed concurrently with the NPN emitter, further including the steps of patterning the mask for such concurrent formation in two stages, by first selectively opening windows for D-MOS drain and NPN collector contacts, followed by selective opening of windows for the emitter and source, in order to reduce mask undercutting and preserve D-MOS alignment.
Claim 4
Dependent Claim
108 words
A process for the monolithic integration of a semiconductor circuit having D-MOS and high performance vertical NPN components, comprising the steps of: (a) providing a monocrystalline p-type semiconductor substrate having a surface layer of isolated n-type semiconductor regions thereon; (b) forming a lightly-doped p-type D-well region in each of selected n-type regions; (c) forming p-type regions constituting the vertical NPN base and the D-MOS gate contact; (d) selectively opening windows in a mask and forming D-MOS drain and NPN collector contacts; and (e) then selectively opening windows in said mask and forming the NPN emitter and D-MOS source, in order to reduce mask undercutting and preserve D-MOS alignment.
Claim 5
Dependent Claim
108 words
A process for the monolithic integration of a semiconductor circuit having D-MOS and high performance vertical NPN components, comprising the steps of: (a) providing a monocrystalline p-type semiconductor substrate having a surface layer of isolated n-type semiconductor regions thereon; (b) forming a lightly-doped p-type D-well region in each of selected n-type regions; (c) forming p-type regions constituting the vertical NPN base and the D-MOS gate contact; (d) selectively opening windows in a mask and forming D-MOS drain and NPN collector contacts; and (e) then selectively opening windows in said mask and forming the NPN emitter and D-MOS source, in order to reduce mask undercutting and preserve D-MOS alignment.
Claim 6
Dependent Claim
29 words
A process as in claim 3 further including the step of controlling the dopant concentrations such that D-MOS threshold is determined by the intersection of emitter and D-well profiles.
Claim 7
Dependent Claim
143 words
A process for the monolithic integration of a semiconductor circuit having a D-MOS component and a vertical bipolar component with independently controlled characteristics, comprising the steps of: (a) providing a monocrystalline semiconductor substrate of one conductivity type having a surface layer of isolated first semiconductor regions of the opposite conductivity type thereon; (b) forming a lightly-doped second region of said one conductivity type in each of selected of said first regions; (c) forming third regions of said one conductivity type constituting the base region of said bipolar component and the D-MOS gate contact; (d) selectively forming fourth and fifth regions of said opposite conductivity type constituting the emitter and collector of said vertical bipolar component; and (e) controlling the dopant concentration in step (b) such that said D-MOS threshold is determined by the intersection of said emitter and said second region dopant profiles.
Claim 8
Dependent Claim
143 words
A process for the monolithic integration of a semiconductor circuit having a D-MOS component and a vertical bipolar component with independently controlled characteristics, comprising the steps of: (a) providing a monocrystalline semiconductor substrate of one conductivity type having a surface layer of isolated first semiconductor regions of the opposite conductivity type thereon; (b) forming a lightly-doped second region of said one conductivity type in each of selected of said first regions; (c) forming third regions of said one conductivity type constituting the base region of said bipolar component and the D-MOS gate contact; (d) selectively forming fourth and fifth regions of said opposite conductivity type constituting the emitter and collector of said vertical bipolar component; and (e) controlling the dopant concentration in step (b) such that said D-MOS threshold is determined by the intersection of said emitter and said second region dopant profiles.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |