Self-aligned metal process for integrated circuit metallization

Claim 1

A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped semiconductor body which separates portions of the conductive layer making the first level contacts to said body comprising: providing said semiconductor body; forming a first insulating layer on a major surface of said body; forming on said layer a polycrystalline silicon layer; forming openings in said polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said second insulating layer to substantially remove said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said semiconductor body; removing the said polycrystalline silicon layer by etching to leave said narrow dimensioned regions on said semiconductor body; and forming a conductive layer on said semiconductor body which has portions thereof electrically separated by said narrow dimensioned regions for contacting in self-alignment regions of said integrated circuits; wherein the said forming a conductive layer includes depositing a blanket layer of conductive material having a thickness of at least about that of the height of the narrow dimensioned regions over said narrow dimensioned regions and areas in between, blanket depositing a plastic material over the said conductive layer to planarize the surface, reactive ion etching the said plastic material and said conductive layer until the tops of said narrow dimensioned regions are reached and removing the remaining said plastic material to thereby form said portions of the conductive layer separated by said narrow dimensioned regions.

Claim 2

A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped semiconductor body which separates portions of the conductive layer making the first level contacts to said body comprising: providing said semiconductor body; forming a first insulating layer on a major surface of said body; forming on said layer a polycrystalline silicon layer; forming openings in said polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said second insulating layer to substantially remove said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said semiconductor body; removing the said polycrystalline silicon layer by etching to leave said narrow dimensioned regions on said semiconductor body; and forming a conductive layer on said semiconductor body which has portions thereof electrically separated by said narrow dimensioned regions for contacting in self-alignment regions of said integrated circuits; wherein the said forming a conductive layer includes depositing a blanket layer of conductive material having a thickness of at least about that of the height of the narrow dimensioned regions over said narrow dimensioned regions and areas in between, blanket depositing a plastic material over the said conductive layer to planarize the surface, reactive ion etching the said plastic material and said conductive layer until the tops of said narrow dimensioned regions are reached and removing the remaining said plastic material to thereby form said portions of the conductive layer separated by said narrow dimensioned regions.

Claim 17

A method for forming bipolar integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped silicon body which separates portions of the conductive layer making the first level contacts to said body comprising: providing a monocrystalline silicon body having regions of dielectric separating surface regions of said monocrystalline silicon from one another; said surface regions containing a surface base region and a subcollector region associated therewith; forming a first insulating layer on the surface of said monocrystalline silicon body having said surface regions; forming on said first insulating layer a polycrystalline silicon layer; forming opening in said polycrystalline silicon layer by reaction ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; said openings are at least located at the locations above which the emitter and collector contact regions are to be formed in said surface regions; forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said second insulating layer to substantially remove said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body; forming said emitter and collector contact regions through the said openings in said polycrystalline silicon layer; removing said polycrystalline layer by etching to leave said narrow dimensioned regions on said silicon body; forming contact openings in said first insulating layer to said emitter, base and collector contact regions; and forming a conductive layer on said silicon body which has portions thereof contacting said emitter, base and collector contact regions on the said surface of said silicon body and electrically separated by said narrow dimension regions; wherein the said forming a conductive layer includes depositing a blanket layer of conductive material having a thickness of at least about that of the height of the narrow dimensioned regions over said narrow dimensioned regions and areas in between, blanket depositing a plastic material over the said conductive layer to planarize the surface, reactive ion etching the said plastic material and said conductive layer until the tops of said narrow dimensioned regions are reached and removing the remaining said plastic material to thereby form portions of the said conductive layer separated by said narrow dimensioned regions.

Claim 18

A method for forming bipolar integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped silicon body which separates portions of the conductive layer making the first level contacts to said body comprising: providing a monocrystalline silicon body having regions of dielectric separating surface regions of said monocrystalline silicon from one another; said surface regions containing a surface base region and a subcollector region associated therewith; forming a first insulating layer on the surface of said monocrystalline silicon body having said surface regions; forming on said first insulating layer a polycrystalline silicon layer; forming opening in said polycrystalline silicon layer by reaction ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; said openings are at least located at the locations above which the emitter and collector contact regions are to be formed in said surface regions; forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said second insulating layer to substantially remove said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body; forming said emitter and collector contact regions through the said openings in said polycrystalline silicon layer; removing said polycrystalline layer by etching to leave said narrow dimensioned regions on said silicon body; forming contact openings in said first insulating layer to said emitter, base and collector contact regions; and forming a conductive layer on said silicon body which has portions thereof contacting said emitter, base and collector contact regions on the said surface of said silicon body and electrically separated by said narrow dimension regions; wherein the said forming a conductive layer includes depositing a blanket layer of conductive material having a thickness of at least about that of the height of the narrow dimensioned regions over said narrow dimensioned regions and areas in between, blanket depositing a plastic material over the said conductive layer to planarize the surface, reactive ion etching the said plastic material and said conductive layer until the tops of said narrow dimensioned regions are reached and removing the remaining said plastic material to thereby form portions of the said conductive layer separated by said narrow dimensioned regions.

Claim 22

A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions on a suitably doped semiconductor body comprising: providing a semiconductor body; forming a first insulating layer on a major surface of said body; forming on said layer a first polycrystalline silicon layer; forming openings in said first polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming a layer of silicon nitride over said substantially horizontal and vertical surfaces; forming a second layer of polycrystalline silicon over said silicon nitride layer on said substantially horizontal and vertical surfaces; reactive ion etching said second layer of polycrystalline silicon to substantially remove said second layer from said horizontal surfaces; thermally oxidizing the remaining said second layer to provide said narrow dimensioned dielectric regions on said silicon body; removing said first polycrystalline layer by etching to leave said narrow dimensioned regions on said silicon body; forming contact openings to said semiconductor body through said first insulating layer; and forming a conductive layer on said semiconductor body which has portions thereof electrically separated by said narrow dimensioned regions for contacting the said integrated circuit through said contact openings.

Claim 23

A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions on a suitably doped semiconductor body comprising: providing a semiconductor body; forming a first insulating layer on a major surface of said body; forming on said layer a first polycrystalline silicon layer; forming openings in said first polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming a layer of silicon nitride over said substantially horizontal and vertical surfaces; forming a second layer of polycrystalline silicon over said silicon nitride layer on said substantially horizontal and vertical surfaces; reactive ion etching said second layer of polycrystalline silicon to substantially remove said second layer from said horizontal surfaces; thermally oxidizing the remaining said second layer to provide said narrow dimensioned dielectric regions on said silicon body; removing said first polycrystalline layer by etching to leave said narrow dimensioned regions on said silicon body; forming contact openings to said semiconductor body through said first insulating layer; and forming a conductive layer on said semiconductor body which has portions thereof electrically separated by said narrow dimensioned regions for contacting the said integrated circuit through said contact openings.

Claim 33

A method for forming bipolar integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped silicon body comprising: providing a monocrystalline silicon body having region of dielectric separating surface regions of said monocrystalline silicon from one another; said surface regions containing a surface base region of a subcollector region associated therewith; forming a first insulating layer on the surface of said monocrystalline silicon body having said surface regions; forming on said first insulating layer a first layer of polycrystalline silicon; forming openings in said first polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surface; said openings are at least located at the locations above which the emitter and collector contact regions are to be formed in said surface regions; thermally oxidizing the exposed polycrystalline silicon surfaces to form a silicon dioxide layer thereon; forming a layer of silicon nitride over said silicon dioxide layer and said substantially horizontal and vertical surfaces; forming a second layer of polycrystalline silicon over said silicon nitride layer on said substantially horizontal and vertical surfaces; reactive ion etching said second layer of polycrystalline silicon to substantially remove said second layer from said horizontal surfaces; thermally oxidizing the remaining said second layer to provide said narrow dimensioned dielectric regions on said silicon body; forming said emitter and collector contact regions through the said openings in said polycrystalline silicon layer; removing said first polycrystalline layer by etching to leave said narrow dielectric regions on said silicon body; forming contact openings in said first insulating layer to said emitter, base and collector contact regions; and forming a conductive layer on said silicon body which has portions thereof contacting said emitter, base and collector contact regions on the said surface of said silicon body and electrically separated by said narrow dimensioned regions.

Claim 34

A method for forming bipolar integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped silicon body comprising: providing a monocrystalline silicon body having region of dielectric separating surface regions of said monocrystalline silicon from one another; said surface regions containing a surface base region of a subcollector region associated therewith; forming a first insulating layer on the surface of said monocrystalline silicon body having said surface regions; forming on said first insulating layer a first layer of polycrystalline silicon; forming openings in said first polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surface; said openings are at least located at the locations above which the emitter and collector contact regions are to be formed in said surface regions; thermally oxidizing the exposed polycrystalline silicon surfaces to form a silicon dioxide layer thereon; forming a layer of silicon nitride over said silicon dioxide layer and said substantially horizontal and vertical surfaces; forming a second layer of polycrystalline silicon over said silicon nitride layer on said substantially horizontal and vertical surfaces; reactive ion etching said second layer of polycrystalline silicon to substantially remove said second layer from said horizontal surfaces; thermally oxidizing the remaining said second layer to provide said narrow dimensioned dielectric regions on said silicon body; forming said emitter and collector contact regions through the said openings in said polycrystalline silicon layer; removing said first polycrystalline layer by etching to leave said narrow dielectric regions on said silicon body; forming contact openings in said first insulating layer to said emitter, base and collector contact regions; and forming a conductive layer on said silicon body which has portions thereof contacting said emitter, base and collector contact regions on the said surface of said silicon body and electrically separated by said narrow dimensioned regions.

Claim 39

The method of claims 31, 32 or 33 wherein said NPN transistors, Schottky barrier devices and resistors are so arranged and interconnected by said conductive layer to form Schottky coupled memory cells in said integrated circuit.

Claim 40

The method for forming bipolar integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped silicon body comprising: providing a monocrystalline silicon body having regions of dielectric separating surface regions of said monocrystalline silicon from one another; said surface regions containing a surface base region and a subcollector region associated therewith; forming a first insulating layer on the surface of said monocrystalline silicon body having said surface regions; forming on said first insulating layer a polycrystalline silicon layer; forming openings in said polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; said openings are at least located at the locations above which base contacts are to be made to said base region and the designated emitter and collector contact regions for said bipolar integrated circuit remains covered with said polycrystalline silicon layer; forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said second insulating layer to substantially remove said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body; removing said polycrystalline layer by etching to leave said narrow dimensioned regions on said silicon body; forming the said emitter regions in the said surface regions of said silicon body; forming contact openings in said first insulating layer to said emitter, base and collector contact regions; and forming a conductive layer on said silicon body which has portions thereof contacting said emitter, base and collector contact regions on the said surface of said silicon body and electrically separated by said narrow dimensioned regions.

Claim 41

The method for forming bipolar integrated circuits having a pattern of narrow dimensioned dielectric regions on a monocrystalline suitably doped silicon body comprising: providing a monocrystalline silicon body having regions of dielectric separating surface regions of said monocrystalline silicon from one another; said surface regions containing a surface base region and a subcollector region associated therewith; forming a first insulating layer on the surface of said monocrystalline silicon body having said surface regions; forming on said first insulating layer a polycrystalline silicon layer; forming openings in said polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; said openings are at least located at the locations above which base contacts are to be made to said base region and the designated emitter and collector contact regions for said bipolar integrated circuit remains covered with said polycrystalline silicon layer; forming a second insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said second insulating layer to substantially remove said second insulating layer from said horizontal surfaces and to provide said narrow dimensioned dielectric regions on said silicon body; removing said polycrystalline layer by etching to leave said narrow dimensioned regions on said silicon body; forming the said emitter regions in the said surface regions of said silicon body; forming contact openings in said first insulating layer to said emitter, base and collector contact regions; and forming a conductive layer on said silicon body which has portions thereof contacting said emitter, base and collector contact regions on the said surface of said silicon body and electrically separated by said narrow dimensioned regions.