Patent US4396980A successfully refreshed from Google Patents.
US4396980A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Combined integrated injection logic and transistor-transistor logic microprocessor integrated circuit design
Assignee: National Semiconductor Corp
•
Filing: 1980-07-11
•
Granted: 1983-08-02
•
Expires: 2000-07-11
Abstract
Abstract A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I2L) and transistor-transistor logic (T2L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T2- I2L interface circuit and structure supplies a T2L input to a plurality of I2L input stages, each having a restricted cross-sectional area resistor element in the base of an I2L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I2L clocking pulse input transistors in a T2L master-slave circuit avoids capacitive coupling problems and allows the master-slave circuit to operate over a much wider temperature range. A cycle counter for the micro-processor integrated circuit implemented as an improved ripple down counter requires a minimum number of gates while avoiding significant delay in operation.
Inventors
- 👤 Hemraj K. Hingarh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01818; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/289; H10; H10D; H10D84/00; H10D84/60; H10D84/65
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
231 words
A microprocessor integrated circuit having a central processing unit which includes a. a data path unit comprising independent address data path circuitry and independent ALU data path circuitry, said address data path circuitry and said ALU data path circuitry being simultaneously operational during a clocked cycle; b. information bus means operatively connected to said data path unit for supplying address and data information thereto and for receiving address and data information therefrom, said information bus means comprising, (i) a bidirectional input/output (I/O) buffer for receiving input information and supplying output information externally of the integrated circuit; and (ii) a bidirectional I/O multiplexer operatively connected (1) to said I/O buffer for receiving I/O multiplexer input information from said I/O buffer and for supplying I/O multiplexer output information to said I/O buffer, (2) to a bus register multiplexer for supplying address and data information thereto, said bus register multiplexer having multiple inputs thereto including an output of said ALU data path circuitry, said bus register multiplexer being operatively connected to both said data path circuitry and said ALU data path circuitry for selectively directing appropriate address or data information thereto and (3) to a bus multiplexer operatively connected to both said address data path circuitry and to said ALU data path circuitry for receiving multiple output signals from said data path circuitry and selectively directing appropriate of said signals to said I/O multiplexer.
Claim 2
Dependent Claim
231 words
A microprocessor integrated circuit having a central processing unit which includes a. a data path unit comprising independent address data path circuitry and independent ALU data path circuitry, said address data path circuitry and said ALU data path circuitry being simultaneously operational during a clocked cycle; b. information bus means operatively connected to said data path unit for supplying address and data information thereto and for receiving address and data information therefrom, said information bus means comprising, (i) a bidirectional input/output (I/O) buffer for receiving input information and supplying output information externally of the integrated circuit; and (ii) a bidirectional I/O multiplexer operatively connected (1) to said I/O buffer for receiving I/O multiplexer input information from said I/O buffer and for supplying I/O multiplexer output information to said I/O buffer, (2) to a bus register multiplexer for supplying address and data information thereto, said bus register multiplexer having multiple inputs thereto including an output of said ALU data path circuitry, said bus register multiplexer being operatively connected to both said data path circuitry and said ALU data path circuitry for selectively directing appropriate address or data information thereto and (3) to a bus multiplexer operatively connected to both said address data path circuitry and to said ALU data path circuitry for receiving multiple output signals from said data path circuitry and selectively directing appropriate of said signals to said I/O multiplexer.
Claim 3
Dependent Claim
38 words
The microprocessor integrated circuit of claim 1 wherein said bidirectional I/O multiplexer is operatively connected to a status register in said ALU data path circuitry for supplying I/O multiplexer output information thereto independently of said bus register multiplexer.
Claim 4
Dependent Claim
26 words
The microprocessor integrated circuit of claim 2 wherein an output of said status register is operatively connected to said bus multiplexer for supplying data information thereto.
Claim 5
Dependent Claim
41 words
The microprocessor integrated circuit of claim 2 wherein said bidirectional I/O multiplexer is operatively connected to an instruction register in a control unit for the microprocessor integrated circuit for supplying I/O multiplexer output information thereto independently of said bus register multiplexer.
Claim 6
Dependent Claim
30 words
The microprocessor integrated circuit of claim 4 wherein said instruction register includes a plurality of outputs connected to appropriate elements of said data path unit for providing control signals thereto.
Claim 7
Dependent Claim
29 words
The microprocessor integrated circuit of claim 3 wherein said bidirectional I/O buffer is operatively connected to a PLA in a control unit for supplying I/O buffer output information thereto.
Claim 8
Dependent Claim
30 words
The microprocessor integrated circuit of claim 6 wherein an output of said PLA is operatively connected to a microprogram register in said control unit for providing control program commands thereto.
Claim 9
Dependent Claim
74 words
The microprocessor integrated circuit of claim 1 wherein said bidirectional I/O buffer includes circuitry for converting TTL (transistor-transistor-logic) level signals to I 2 L (integrated-injection logic) level signals for use by I 2 L elements in said integrated circuit and converting I 2 L level outputs from I 2 L elements in said integrated circuit to TTL level signals for use by TTL elements in said integrated circuit or externally of said integrated circuit.
Claim 10
Dependent Claim
129 words
The microprocessor integrated circuit of claim 1 wherein said integrated circuit comprises TTL portions and an I 2 L portion and further including a TTL-to-I 2 L interface comprising: a TTL output stage operatively connected to said TTL portions; and a plurality of I 2 L input stages, each of which includes a bipolar transistor having an emitter coupled to a predetermined potential, a plurality of collectors, and a base coupled through a resistive element to said output stage for receiving an output signal from said output stage, each resistive element comprising a pair of regions of semiconductor material of a given conductivity type joined by a third region of semiconductor material of the given conductivity type having a cross-sectional area smaller than that of either of the pair.
Claim 11
Dependent Claim
59 words
The microprocessor integrated circuit of claim 9 wherein said ALU data path circuitry includes a first storage register comprising a first plurality of interconnected flip-flop circuits, output control circuitry being associated with each flip-flop circuit for selectively directing an output signal thereof to either a source or a destination input to an ALU of the ALU data path circuitry.
Claim 12
Dependent Claim
120 words
The microprocessor integrated circuit of claim 10 wherein said ALU data path circuitry includes a second storage register comprising a second plurality of flip-flop circuits each comprising a first latch responsive to a clock input signal and a data input signal, a second latch responsive to the clock input signal and a signal complementary to the data input signal, a third latch having a first output terminal for providing a first output signal and a second output terminal for providing a second output signal complementary to the first output signal, and a first transistor having an output electrode coupled to the first output terminal and an input parallel with an input electrode of a cross-coupled transistor in the first latch.
Claim 13
Dependent Claim
70 words
The microprocessor integrated circuit of claim 11 wherein each flip-flop circuit of the second plurality of flip-flop circuits includes a second transistor having an output electrode coupled to the second output terminal of that flip-flop circuit and an input electrode responsive to the clock input signal for that flip-flop circuit and coupled in parallel with an input electrode of a cross-coupled transistor in the second latch of that flip-flop circuit.
Claim 14
Dependent Claim
48 words
The microprocessor integrated circuit of claim 12 further including a timing unit having a transistor-transistor logic master-slave flip-flop circuit comprising a master flip-flop and a slave flip-flop, the master flip-flop circuit having a pair of bipolar transistors coupled between a source of clocking pulses and the slave flip-flop.
Claim 15
Dependent Claim
71 words
The microprocessor integrated circuit of claim 13 wherein said ALU data path circuitry includes a cycle counter comprising a third plurality of flip-flop circuits sequentially interconnected to operate as a ripple-down counter, an output terminal of the first one of each pair of consecutive ones of the third plurality of flip-flop circuits being coupled to two input terminals of the other of that pair for supplying two clock signals respectively thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-01 | 1987-01-31 | 1987-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-01 | 1991-01-31 | 1991-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-01 | 1995-01-31 | 1995-08-02 | $7700.00 | Window Closed / Lapsed |