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US4394657A
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Decoder circuit
Assignee: Fujitsu Ltd
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Filing: 1980-12-18
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Granted: 1983-07-19
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Expires: 2000-12-18
Abstract
Abstract A decoder circuit comprises input gates, a logic circuit for generating an output according to input signals, an output gate for driving a word line, and a current control device for activating the output gate according to the output of the logic circuit.
Inventors
- 👤 Hideaki Isogai
- 👤 Yukio Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:59
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C11/413; G11C11/414; G11C11/415; G11C8/06; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K5/00; H03K5/15
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
200 words
A decoder circuit, operatively connectable to receive a plurality input signals "a 0 , a 1 , a 2 , - - - , a i " and to a word line, comprising: input gates, operatively connectable to receive the plurality of input signals "a 0 , a 1 , a 2 , - - - , a i ", for generating inverse signals "a 0 , a 1 , a 2 , - - - , a i " in dependence upon the plurality of input signals "a 0 , a 1 , a 2 , - - - , a i "; a logic circuit, operatively connected to said input gates, for generating an output in dependence upon combined input signals that are the combination signals of said signals a 0 through a i and a 0 through a i ; an output gate, operatively connected to said logic circuit and operatively connectable to the word line, for selectively driving the word line by the output supplied from said logic circuit; and current control means, electrically connected between a voltage source and said output gate, for switching a current from said voltage source and activating said output gate.
Claim 2
Dependent Claim
200 words
A decoder circuit, operatively connectable to receive a plurality input signals "a 0 , a 1 , a 2 , - - - , a i " and to a word line, comprising: input gates, operatively connectable to receive the plurality of input signals "a 0 , a 1 , a 2 , - - - , a i ", for generating inverse signals "a 0 , a 1 , a 2 , - - - , a i " in dependence upon the plurality of input signals "a 0 , a 1 , a 2 , - - - , a i "; a logic circuit, operatively connected to said input gates, for generating an output in dependence upon combined input signals that are the combination signals of said signals a 0 through a i and a 0 through a i ; an output gate, operatively connected to said logic circuit and operatively connectable to the word line, for selectively driving the word line by the output supplied from said logic circuit; and current control means, electrically connected between a voltage source and said output gate, for switching a current from said voltage source and activating said output gate.
Claim 3
Dependent Claim
17 words
A decoder circuit as claimed in claim 1, wherein said current control means comprises a PNP transistor.
Claim 4
Dependent Claim
19 words
A decoder circuit as claimed in claim 1, wherein said logic circuit comprises a multi-emitter transistor comprising an AND-circuit.
Claim 5
Dependent Claim
47 words
A decoder circuit as claimed in claim 1, wherein said decoder circuit further comprises: voltage clamping means, operatively connected to said output gate, for clamping an input voltage of said output gate; and biasing means, electrically connected to said voltage clamping means, for biasing said output gate.
Claim 6
Dependent Claim
131 words
A decoder circuit for a word line, operatively connectable to receive input bit signals, said decoder circuit comprising: an input gate, operatively connectable to receive the input bit signals, for generating gate signals and inverted gate signals; a logic gate, operatively connected to said input gate, for generating a logic signal in dependence upon predetermined ones of the gate signals and the inverted gate signals; a current switch, operatively connected to said logic gate, for passing current therethrough in dependence upon the logic signal; current control means, operatively connected to said current switch at a first node, for controlling current flow in dependence upon the current from said current switch; and a word line driver, operatively connected to said current control means at a second node, for driving the word line.
Claim 7
Dependent Claim
131 words
A decoder circuit for a word line, operatively connectable to receive input bit signals, said decoder circuit comprising: an input gate, operatively connectable to receive the input bit signals, for generating gate signals and inverted gate signals; a logic gate, operatively connected to said input gate, for generating a logic signal in dependence upon predetermined ones of the gate signals and the inverted gate signals; a current switch, operatively connected to said logic gate, for passing current therethrough in dependence upon the logic signal; current control means, operatively connected to said current switch at a first node, for controlling current flow in dependence upon the current from said current switch; and a word line driver, operatively connected to said current control means at a second node, for driving the word line.
Claim 8
Dependent Claim
28 words
A decoder circuit as claimed in claim 5, wherein said current control means comprises a transistor operatively connected to said current switch and to said word line driver.
Claim 9
Dependent Claim
25 words
A decoder circuit as claimed in claim 5, further comprising a constant voltage circuit, operatively connected to the first node, for generating a constant voltage.
Claim 10
Dependent Claim
55 words
A decoder circuit as claimed in claim 5, wherein said word line driver has an input, said decoder circuit further comprising: a parallel circuit operatively connected to the second node; and a biasing circuit operatively connected to said parallel circuit, so that the input of said word line driver is maintained at a predetermined voltage.
Claim 11
Dependent Claim
27 words
A decoder circuit as claimed in claim 5, wherein said logic gate comprises an AND gate operatively connected to said input gate and to said current switch.
Claim 12
Dependent Claim
27 words
A decoder circuit as claimed in claim 5, wherein said logic gate comprises a multiemitter transistor operatively connected to said input gate and to said current switch.
Claim 13
Dependent Claim
27 words
A decoder circuit as claimed in claim 5, wherein said logic gate comprises a pair of diodes operatively connected between said input gate and said current switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-18 | 1987-01-17 | 1987-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-18 | 1991-01-17 | 1991-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-18 | 1995-01-17 | 1995-07-19 | $7700.00 | Window Closed / Lapsed |