Temperature responsive refresh control circuit

Claim 2

A memory circuit comprising a memory cell array including a plurality of memory cells, each of said memory cells storing data in a dynamic manner; an oscillator for generating an oscillation signal having a frequency characteristic with a positive temperature coefficient, said oscillator including a first terminal receiving a first potential, a second terminal receiving a second potential, an output terminal from which said oscillation signal is derived, first to third nodes, a first resistor made of polycrystalline silicon and coupled between said first terminal and said first node, a second resistor made of polycrystalline silicon and coupled between said first terminal and said second node, a first capacitor coupled between said first node and said second terminal, a second capacitor coupled between said second node and said second terminal, a first field effect transistor coupled beteen said first node and said second terminal and having a gate coupled to said third node, a second field effect transistor coupled between said second node and said second terminal and having a gate coupled to said first node, a third field effect transistor coupled between said third node and said second terminal and having a gate coupled to said second node, a fourth field effect transistor coupled between said first terminal and said third node, a third capacitor coupled between said third node and a gate of said fourth transistor, a fifth field effect transistor coupled between said first terminal and the gate of said fourth transistor and having a gate coupled to said first terminal, and means for connecting said third node to said output terminal; and refresh means responsive to said oscillation signal for operatively refreshing at least one of said memory cells.

Claim 3

The circuit according to claim 1, in which each of said memory cells includes a storage capacitor and a transfer field effect transistor connected in series with said storage capacitor.

Claim 4

The circuit according to claim 1, in which said memory cells are arrayed in rows and columns and each refresh operation is performed on the memory cells coupled to one of said rows.

Claim 5

A memory circuit comprising a plurality of memory cells of a dynamic type; oscillator means for generating a periodic signal, the frequency of said periodic signal increasing in accordance with an increase in atmospheric temperature, said oscillator means including a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, a first series circuit of a resistor made of a polycrystalline silicon and a capacitor, means for connecting one end of said first series circuit to said first terminal, means for connecting the other end of said first series circuit to said second terminal, a second series circuit of a resistor made of a polycrystalline silicon and a capacitor, means for connecting one end of said second series circuit to said first terminal, means for connecting the other end of said second series circuit to said second terminal, a first inverter, means for connecting an output terminal of said first inverter to an intermediate junction of said first series circuit, a second inverter, means for connecting an output terminal of said second inverter to an intermediate junction of said second series circuit, means for connecting the intermediate junction of said first series circuit to an input terminal of said second inverter, a third inverter circuit of an input field effect transistor and a load circuit connected in series at an intermediate node, said load circuit having a first field effect transistor coupled between said first terminal and said intermediate node, a capacitor coupled between said intermediate node and a gate of said first transistor, and a second field effect transistor coupled between said first terminal and the gate of said first transistor and having a gate coupled to said first terminal, means for connecting said intermediate node to an input terminal of said first inverter, an output terminal from which said periodic signal is derived, and means for connecting said output terminal to said intermediate node; means for generating a refresh command signal based on said periodic signal; and refresh means for operatively refreshing at least one of said memory cells in response to said refresh command signal.

Claim 6

A memory circuit comprising a plurality of memory cells of a dynamic type; oscillator means for generating a periodic signal, the frequency of said periodic signal increasing in accordance with an increase in atmospheric temperature, said oscillator means including a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, a first series circuit of a resistor made of a polycrystalline silicon and a capacitor, means for connecting one end of said first series circuit to said first terminal, means for connecting the other end of said first series circuit to said second terminal, a second series circuit of a resistor made of a polycrystalline silicon and a capacitor, means for connecting one end of said second series circuit to said first terminal, means for connecting the other end of said second series circuit to said second terminal, a first inverter, means for connecting an output terminal of said first inverter to an intermediate junction of said first series circuit, a second inverter, means for connecting an output terminal of said second inverter to an intermediate junction of said second series circuit, means for connecting the intermediate junction of said first series circuit to an input terminal of said second inverter, a third inverter circuit of an input field effect transistor and a load circuit connected in series at an intermediate node, said load circuit having a first field effect transistor coupled between said first terminal and said intermediate node, a capacitor coupled between said intermediate node and a gate of said first transistor, and a second field effect transistor coupled between said first terminal and the gate of said first transistor and having a gate coupled to said first terminal, means for connecting said intermediate node to an input terminal of said first inverter, an output terminal from which said periodic signal is derived, and means for connecting said output terminal to said intermediate node; means for generating a refresh command signal based on said periodic signal; and refresh means for operatively refreshing at least one of said memory cells in response to said refresh command signal.

Claim 7

The circuit according to claim 4, in which said refresh means includes a flip-flop adapted to be set by said refresh command signal, and internal address means responsive to the set state of said flip-flop for sequentially generating internal address signals.

Claim 8

A memory circuit comprising a memory cell array including: a plurality of dynamic type memory cells; address means for receiving an external address signal; an oscillator circuit for generating an oscillation signal, a frequency of said oscillation signal increasing substantially in proportion to a rise in a temperature, said oscillator circuit including a first terminal receiving a first potential, a second terminal receiving a second potential, an output terminal from which said oscillation signal is derived, first to third nodes, a first resistor made of polycrystalline silicon and coupled between said first terminal and said first node, a second resistor made of polycrystalline silicon and coupled between said first terminal and said second node, a first capacitor coupled between said first node and said second terminal, a second capacitor coupled between said second node and said second terminal, a first field effect transistor coupled between said first node and said second terminal and having a gate coupled to said third node, a second field effect transistor coupled between said second node and said second terminal and having a gate coupled to said first node, a third field effect transistor coupled between said third node and said second terminal and having a gate coupled to said second node, a fourth field effect transistor coupled between said first terminal and said third node, a third capacitor coupled between said third node and a gate of said fourth transistor, a fifth field effect transistor coupled between said first terminal and the gate of said fourth transistor and having a gate coupled to said first terminal and means for connecting said third node to said output terminal; a bistable circuit having first and second states, said bistable circuit taking the first state in response to said oscillation signal; internal address means responsive to the first state of said bistable circuit for generating an internal address signal; multiplex means coupled to said address means and said internal address means; access means coupled to said multiplex means for selectively making at least one of said memory cells in readable condition, said multiplex means transferring the internal address signal and the external address signal to said access means in response to the first state and the second state of said bistable circuit, respectively; and reset means responsive to said internal address means for setting said bistable circuit in the second state.

Claim 9

A memory circuit comprising a memory cell array including: a plurality of dynamic type memory cells; address means for receiving an external address signal; an oscillator circuit for generating an oscillation signal, a frequency of said oscillation signal increasing substantially in proportion to a rise in a temperature, said oscillator circuit including a first terminal receiving a first potential, a second terminal receiving a second potential, an output terminal from which said oscillation signal is derived, first to third nodes, a first resistor made of polycrystalline silicon and coupled between said first terminal and said first node, a second resistor made of polycrystalline silicon and coupled between said first terminal and said second node, a first capacitor coupled between said first node and said second terminal, a second capacitor coupled between said second node and said second terminal, a first field effect transistor coupled between said first node and said second terminal and having a gate coupled to said third node, a second field effect transistor coupled between said second node and said second terminal and having a gate coupled to said first node, a third field effect transistor coupled between said third node and said second terminal and having a gate coupled to said second node, a fourth field effect transistor coupled between said first terminal and said third node, a third capacitor coupled between said third node and a gate of said fourth transistor, a fifth field effect transistor coupled between said first terminal and the gate of said fourth transistor and having a gate coupled to said first terminal and means for connecting said third node to said output terminal; a bistable circuit having first and second states, said bistable circuit taking the first state in response to said oscillation signal; internal address means responsive to the first state of said bistable circuit for generating an internal address signal; multiplex means coupled to said address means and said internal address means; access means coupled to said multiplex means for selectively making at least one of said memory cells in readable condition, said multiplex means transferring the internal address signal and the external address signal to said access means in response to the first state and the second state of said bistable circuit, respectively; and reset means responsive to said internal address means for setting said bistable circuit in the second state.