Patent US4389660A successfully refreshed from Google Patents.
US4389660A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High power solid state switch
Assignee: Boeing North American Inc
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Filing: 1980-07-31
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Granted: 1983-06-21
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Expires: 2000-07-31
Abstract
Abstract Disclosed is an integrated dual gate switch which is fabricated on a semi-insulating GaAs substrate. A metallic input line is deposited on the substrate and coupled to an ion implanted n-type region in the substrate through a first ohmic contact. A metallic output line is spaced from the input line and coupled through a second ohmic contact to the n-type region. A first metallic gate is deposited on the substrate between the input and output lines, while a second metallic gate is deposited between the first gate and the output line. A first capacitive coupling between the input line and the first gate includes a first metallic conductor deposited on the substrate and overlapping portions of the input line and first gate, and a first dielectric layer between the first gate and the first conductor. A similar second capacitive coupling between the output line and the second gate includes a second metallic conductor and a second dielectric layer.
Inventors
- 👤 D. Richard Decker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/873
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
244 words
An integrated dual gate switch fabricated on a semi-insulating substrate, comprising: a region of one conductivity type in said substrate; an input line on said substrate and coupled to said region by a first ohmic contact; an output line on said substrate spaced from said input line and coupled to said region by a second ohmic contact; a first gate on said substrate between said input line and said output line; a second gate on said substrate between said first gate and said output line, said first and second gates being biassed in the on state of said switch at no less than 0 Volts with respect to said input and output lines; a first capacitive coupling between said input line and said first gate, including: a first conductor on said substrate and overlapping a portion of said input line and a portion of said first gate; and a first dielectric layer between said first gate and said first conductor; and a second capacitive coupling between said output line and said second gate, including: a second conductor on said substrate and overlapping a portion of said output line and a portion of said second gate; and a second dielectric layer between said second gate and said second conductor, whereby any AC voltage appearing across said switch in the off state will be coupled to said first and second gates by said first and second capacitive couplings to maintain said switch in the off state.
Claim 2
Dependent Claim
244 words
An integrated dual gate switch fabricated on a semi-insulating substrate, comprising: a region of one conductivity type in said substrate; an input line on said substrate and coupled to said region by a first ohmic contact; an output line on said substrate spaced from said input line and coupled to said region by a second ohmic contact; a first gate on said substrate between said input line and said output line; a second gate on said substrate between said first gate and said output line, said first and second gates being biassed in the on state of said switch at no less than 0 Volts with respect to said input and output lines; a first capacitive coupling between said input line and said first gate, including: a first conductor on said substrate and overlapping a portion of said input line and a portion of said first gate; and a first dielectric layer between said first gate and said first conductor; and a second capacitive coupling between said output line and said second gate, including: a second conductor on said substrate and overlapping a portion of said output line and a portion of said second gate; and a second dielectric layer between said second gate and said second conductor, whereby any AC voltage appearing across said switch in the off state will be coupled to said first and second gates by said first and second capacitive couplings to maintain said switch in the off state.
Claim 3
Dependent Claim
12 words
The switch of claim 1, wherein said semi-insulating substrate comprises semi-insulating GaAs.
Claim 4
Dependent Claim
12 words
The switch of claim 2, wherein said region is of n-type conductivity.
Claim 5
Dependent Claim
23 words
The switch of claim 3, wherein said region further comprises a layer in said substrate which is ion implanted with an n-type dopant.
Claim 6
Dependent Claim
22 words
The switch of claim 1, wherein each of said input and output lines further comprises a metallic line deposited on said substrate.
Claim 7
Dependent Claim
29 words
The switch of claim 5, wherein said gates each further comprise a metallic layer deposited on said substrate to establish a Schottky barrier between each gate and said substrate.
Claim 8
Dependent Claim
234 words
An integrated dual gate switch fabricated on a semi-insulating substrate, comprising: a region of one conductivity type in said substrate; an input line on said substrate and coupled to said region; an output line on said substrate spaced from said input line and coupled to said region; a first gate on said substrate between said input line and said output line; a second gate on said substrate between said first gate and said output line, said first and second gates being biassed in the on state of said switch at no less than 0 Volts with respect to said input and output lines; a first capacitive coupling between said input line and said first gate, including: a first conductor on said substrate and overlapping a portion of said input line and a portion of said first gate, and a first dielectric layer between said first gate and said first conductor; and a second capacitive coupling between said output line and said second gate, including: a second conductor on said substrate and overlapping a portion of said output line and a portion of said second gate, and a second dielectric layer between said second gate and said second conductor, whereby any AC voltage appearing across said switch in the off state will be coupled to said first and second gates by said first and second capacitive couplings to maintain said switch in the off state.
Claim 9
Dependent Claim
234 words
An integrated dual gate switch fabricated on a semi-insulating substrate, comprising: a region of one conductivity type in said substrate; an input line on said substrate and coupled to said region; an output line on said substrate spaced from said input line and coupled to said region; a first gate on said substrate between said input line and said output line; a second gate on said substrate between said first gate and said output line, said first and second gates being biassed in the on state of said switch at no less than 0 Volts with respect to said input and output lines; a first capacitive coupling between said input line and said first gate, including: a first conductor on said substrate and overlapping a portion of said input line and a portion of said first gate, and a first dielectric layer between said first gate and said first conductor; and a second capacitive coupling between said output line and said second gate, including: a second conductor on said substrate and overlapping a portion of said output line and a portion of said second gate, and a second dielectric layer between said second gate and said second conductor, whereby any AC voltage appearing across said switch in the off state will be coupled to said first and second gates by said first and second capacitive couplings to maintain said switch in the off state.
Claim 10
Dependent Claim
22 words
The switch of claim 7, where each of said input and output lines further comprises a metallic line deposited on said substrate.
Claim 11
Dependent Claim
31 words
The switch of claim 8, wherein each of said gates comprises a metallic layer deposited on said substrate to establish a Schottky barrier between each of said gates and said substrate.
Claim 12
Dependent Claim
256 words
An integrated dual gate switch fabricated on a semi-insulating GaAs substrate, comprising: an n-type region ion implanted in said substrate; a metallic input line deposited on said substrate and coupled to said region by a first ohmic contact; a metallic output line deposited on said substrate, spaced from said input line, and coupled to said region by a second ohmic contact; a first metallic gate deposited on said substrate between said input line and said output line; a second metallic gate deposited on said substrate between said first gate and said output line, said first and second gates being biassed in the on state of said switch at no less than 0 Volts with respect to said input and output lines; a first capacitive coupling between said input line and said first gate, including: a first metallic conductor deposited on said substrate and overlapping a portion of said input line and a portion of said first gate, and a first dielectric layer between said first gate and said first conductor; and a second capacitive coupling between said output line and said second gate, including: a second metallic conductor deposited on said substrate and overlapping a portion of said input line and a portion of said second gate, and a second dielectric layer between said second gate and said second conductor, whereby any AC voltage appearing across said switch in the off state will be coupled to said first and second gates by said first and second capacitive couplings to maintain said switch in the off state.
Claim 13
Dependent Claim
256 words
An integrated dual gate switch fabricated on a semi-insulating GaAs substrate, comprising: an n-type region ion implanted in said substrate; a metallic input line deposited on said substrate and coupled to said region by a first ohmic contact; a metallic output line deposited on said substrate, spaced from said input line, and coupled to said region by a second ohmic contact; a first metallic gate deposited on said substrate between said input line and said output line; a second metallic gate deposited on said substrate between said first gate and said output line, said first and second gates being biassed in the on state of said switch at no less than 0 Volts with respect to said input and output lines; a first capacitive coupling between said input line and said first gate, including: a first metallic conductor deposited on said substrate and overlapping a portion of said input line and a portion of said first gate, and a first dielectric layer between said first gate and said first conductor; and a second capacitive coupling between said output line and said second gate, including: a second metallic conductor deposited on said substrate and overlapping a portion of said input line and a portion of said second gate, and a second dielectric layer between said second gate and said second conductor, whereby any AC voltage appearing across said switch in the off state will be coupled to said first and second gates by said first and second capacitive couplings to maintain said switch in the off state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-20 | 1986-12-20 | 1987-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-20 | 1990-12-20 | 1991-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-20 | 1994-12-20 | 1995-06-21 | $7700.00 | Window Closed / Lapsed |