System for preventing transient induced errors in phase locked loop

Claim 3

The method according to claim 1 wherein said phase detector provides phase comparison based on positive zero crossings of a VCO derived signal and said periodic control signal.

Claim 5

The method according to claim 3 wherein said timing signals are derived by counting down the output of the VCO of the phase-locked loop.

Claim 6

The method according to claim 3 wherein said timing signals are derived by dividing the frequency of the VCO to equal the frequency of said control signal.

Claim 7

The method according to claim 5 wherein the frequency of said control signal is 60 Hz.

Claim 8

The method according to claim 1 further comprising the step of overriding said enabling and disabling steps and reenabling the control signal input to said phase detector when said phase-locked loop is detected to be substantially out of lock.

Claim 9

The method of claim 7 further comprising the step of re-establishing the normal control of said enabling and disabling steps when said phase-locked loop regains lock.

Claim 12

The system according to claim 9 wherein said control means further comprises phase detector input logic circuit means which allows only the first of any control signals received during any given enable time window to be passed to the sequential phase detector as a signal usable by said phase detector.

Claim 13

The system according to either claim 9 or 10 wherein said control means further comprises, overriding circuit means including auxiliary phase detecting means for overriding said enabling and disabling means to re-enable said control signal prior to said time window as an input to said phase detector when said phase-locked loop is detected as being substantially out of lock with said control signal by said auxiliary phase detecting means.

Claim 14

The system according to claim 9 wherein said time window is equal to or greater than the dynamic phase error of the system.

Claim 15

The system according to claim 9 wherein said control means for controlling said enabling and disabling means further comprises: timing means for deriving timing signals related to the frequency of the said input control signal and the VCO of the phase-locked loop; logic circuit means for utilizing the output signals of said timing means to accomplish said enable and disable control functions.

Claim 16

The system according to claim 13 wherein said timing means is driven from the VCO of the phase-locked loop.

Claim 18

The system according to claim 15 wherein said VCO signal is counted down to the frequency of said control signal.

Claim 19

The system according to claim 16 wherein said frequency is 60 Hz.

Claim 20

The system according to claim 15 wherein said control signal is derived from a 60 Hz AC line input.

Claim 21

The system according to claim 15 wherein said enabling logic circuit means further comprises: first gate means adapted to be turned on upon receiving a signal indicating that said counting means has reached the beginning of said enable time window; and second gate means having a first input derived from the output of said first gate means and a second input comprising control signal from said control signal generating means such that a high first signal combined with a control signal enables said second gate means, said second gate means having an output connected to the phase detector input logic circuit means; and wherein said control means further comprises: phase detector input logic circuit means connected between the output of said second gate means and the control signal input of said phase detector, wherein said phase detector input logic circuit means is adapted to transmit a logic input signal to said phase detector responsive only to the first signal from said second gate means during any given enable period.

Claim 22

The apparatus according to claim 19 wherein said first and second gate means are AND gates and said phase detector input logic circuit means is a flip-flop.

Claim 23

The system according to claim 19 wherein said logic circuit means for disabling said control signal input comprises means responsive to the reset signal output of said counting means for disabling the input to said second gate means derived from the output of first gate means and resetting and thereby reenabling said phase detector input logic means.

Claim 24

The system according to claim 21 wherein said second gate is disabled prior to the reenabling of said phase detector input logic means to prevent the transmission of spurious input signals during that interim.

Claim 25

The system of claim 21 wherein said means responsive to the reset output of said counting means further comprises: first bistable circuit element having an input connected to the reset signal output of said counting means and having an output which resets said phase detector input logic circuit means; and second bistable circuit element connected between said first and second gate means.

Claim 26

The system according to claim 22 wherein said overriding circuit means further comprises: output comparator means having a threshold output indicative of an out-of-lock condition beyond the maximum desired for the phase-locked loop to operate, said output of said output comparator means being utilized as an overriding signal for continuously enabling said control signal as an input to said phase detector until said phase lock is reestablished and said comparator signal is disabled.

Claim 29

An FSK digital logic transmitter system for transmitting data via power line carrier comprising: a phase-locked loop having a sequential phase detector; means for FSK modulating the frequency of the VCO of the phase locked loop to produce output signals indicative of digital logic; output amplification means for amplifying said output signals and transferring said output signals to the powerline; means for minimizing synchronization errors in said phase-locked loop having said sequential phase detector for determining the phase difference between the output of the VCO of the phase-locked loop and a periodic control signal having a characteristic control signal cycle period further comprising: VCO signal input means for providing an input to said sequential phase detector indicative of the phase state of said VCO; control signal generating means for providing a periodic control signal indicative of the phase state of a control signal of known frequency derived from without said phase-locked loop; enabling means for enabling said control signal as an input to said sequential phase detector for a relatively short enable time window which comprises a small fraction of the control signal cycle period, said enable time window beginning just before a control signal is anticipated; disabling means for disabling said control signal input to said phase detector for the remainder of said control signal cycle period; and control means for controlling said enabling and disabling means, said control means further comprising: phase detector input logic circuit means which allows only the first of any control signals received during any given enable time interval to be passed to the sequential phase detector as a signal usable by said phase detector; and overriding circuit means including auxiliary phase detecting means for overriding said enabling and disabling means to re-enable said control signal prior to said time window as an input to said phase detector when said phase-locked loop is detected as being substantially out of lock with said control signal by said auxiliary phase detecting means; timing means for deriving timing signals related to the frequency of the said input control signal and the VCO of the phase-locked loop; logic circuit means for utilizing the output signals of said timing means to accomplish said enable, disable and override control functions.

Claim 30

An FSK digital logic transmitter system for transmitting data via power line carrier comprising: a phase-locked loop having a sequential phase detector; means for FSK modulating the frequency of the VCO of the phase locked loop to produce output signals indicative of digital logic; output amplification means for amplifying said output signals and transferring said output signals to the powerline; means for minimizing synchronization errors in said phase-locked loop having said sequential phase detector for determining the phase difference between the output of the VCO of the phase-locked loop and a periodic control signal having a characteristic control signal cycle period further comprising: VCO signal input means for providing an input to said sequential phase detector indicative of the phase state of said VCO; control signal generating means for providing a periodic control signal indicative of the phase state of a control signal of known frequency derived from without said phase-locked loop; enabling means for enabling said control signal as an input to said sequential phase detector for a relatively short enable time window which comprises a small fraction of the control signal cycle period, said enable time window beginning just before a control signal is anticipated; disabling means for disabling said control signal input to said phase detector for the remainder of said control signal cycle period; and control means for controlling said enabling and disabling means, said control means further comprising: phase detector input logic circuit means which allows only the first of any control signals received during any given enable time interval to be passed to the sequential phase detector as a signal usable by said phase detector; and overriding circuit means including auxiliary phase detecting means for overriding said enabling and disabling means to re-enable said control signal prior to said time window as an input to said phase detector when said phase-locked loop is detected as being substantially out of lock with said control signal by said auxiliary phase detecting means; timing means for deriving timing signals related to the frequency of the said input control signal and the VCO of the phase-locked loop; logic circuit means for utilizing the output signals of said timing means to accomplish said enable, disable and override control functions.