Communication system for distributed control arrangement

Claim 2

In a communication system for a distributed control arrangement adapted to control the operation of a plurality of operating units of a common installation, each of said operating units being under the control of a set of subsystems adapted to perform specific control functions relative to the corresponding operating unit; a plurality of communication nodes each corresponding to a separate one of said operating units, each of said nodes being coupled to the set of subsystems that exercise control over the corresponding operating unit; a separate secondary station coupled to each of said nodes; each of said nodes including a common node bus; the secondary station and respective ones of the set of subsystems associated with a node individually constituting separate circuits external to said node, each of said external circuits including a local data processor and being adapted to communicate through said node bus; a data link interconnecting respective nodes through the secondary station associated with each node; and a primary station coupled to said data link and including a data processor, said primary station being adapted to address respective ones of said secondary stations through said data link in accordance with a predetermined protocol and a sequence determined by said primary station; whereby said primary station upon its own command is capable of communicating with respective ones of a selectively variable number of nodes coupled to said data link to transmit or receive information with respect to selected subsystems associated with each of said nodes, said primary station being adapted to prevent contention between competing nodes for access to said data link.

Claim 3

A system in accordance with claim 1 wherein each of said nodes further comprises: a controller coupled to said common node bus; a plurality of port buffers each coupled to said bus and to a separate one of said external circuits, each of said port buffers being adapted to establish a 2-stage bidirectional transfer link between its coupled external circuit and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the protocol of the external circuit and the protocol of said node; and said controller including means for sequentially polling said port buffers; whereby said controller periodically sets the conditions for each port buffer to establish its transfer link.

Claim 4

A system in accordance with claim 2 wherein one stage of each of said transfer links comprises means for providing bidirectional data transfers between the coupled external circuit and its corresponding port buffer timed by said external circuit; and wherein the second stage of each of said transfer links comprises means for providing bidirectional data transfers between said port buffer and said controller by way of said bus timed by said controller.

Claim 5

A system in accordance with claim 3 wherein said one stage of each of said transfer links is further adapted to perform data transfers from the coupled external circuit to its corresponding port buffer under port buffer control.

Claim 6

A system in accordance with claim 4 wherein said controller includes means for generating clock pulses; said means for providing data transfers in said second stage of each of said transfer links timed by said controller including means for transferring said information in clock pulse synchronism; and wherein data transfers in said one stage of each of said transfer links may be performed asynchronously with respect to said clock pulses.

Claim 7

A system in accordance with claim 4 wherein said intermediate data storage in each of said port buffers comprises a port buffer memory; each of said port buffers further comprising: first bidirectional switch means connected between said port buffer memory and the corresponding external circuit; second bidirectional switch means connected between said port buffer memory and said controller; and means for enabling said first and second switch means during mutually exclusive time intervals to stagger the data transfer operations in the respective stages of said transfer link.

Claim 8

A system in accordance with claim 6 wherein data and control information is organized into bytes, each data transfer between an external circuit and said controller being preceded by a pair of control bytes generated by said subsystem; each of said port buffers further comprising: latch means for temporarily storing said control bytes; and means operative during each data transfer for directing said control bytes into said latch means and for directing said data bytes into said port buffer memory through one of said switch means.

Claim 9

A system in accordance with claim 7 wherein said control bytes define at least the direction of the data transfer and the number count of data bytes to be transferred; each of said port buffers further comprising: means responsive to said defined direction of data transfer to determine the order in which said first and second switch means are enabled; means operative during data transfers performed under port buffer control for counting the number of data bytes transferred; means for comparing the count of transferred data bytes with said number count entered by said control bytes; and means for terminating the transfer of data bytes when equality of the compared counts is reached.

Claim 10

A system in accordance with claim 8 wherein said control bytes further define a starting address; said controller comprising: means for generating clock pulses; a controller memory; said means timed by said controller including a controller address counter for sequentially addressing successive controller memory locations in clock pulse synchronism, said controller address counter being responsive to said control bytes to begin said sequential addressing at said starting address; and means responsive to said defined direction of data transfer to write said data bytes into, or to read said data bytes out from, said addressed controller memory locations.

Claim 11

A system in accordance with claim 4 or 9 wherein said control bytes are loaded into each port buffer by control signals generated by the corresponding external circuit; each of said port buffers comprising means responsive to said control signals and to said defined direction of data transfer to generate a transfer request; said sequential polling means comprising a port address counter for generating signals adapted to address successive port buffers of said node; means for initiating the requested data transfer if a transfer request generated by a port buffer is pending when said port buffer is addressed in sequence by said port address counter; and means for interrupting said sequential addressing of said port buffers for the duration of each data transfer; whereby contention between competing port buffers for access to said common node bus is effectively prevented by said controller.

Claim 12

A system in accordance with claim 10 wherein said external circuits of at least one of said nodes further include at least one peripheral station adapted to communicate through said node; said last-recited node further comprising a port buffer corresponding to said peripheral station; and each of said port buffers including means for decoding the count of said port address counter, said port buffers being substantially identical to each other except for said decoding means.

Claim 13

A communication node for enabling a set of subsystems external to said node to communicate through the latter, each of said subsystems comprising a circuit including local data processing means for performing a specific control function relative to an operating unit responsive to said set of subsystems; said communication node comprising: a common node bus; a controller coupled to said bus; a plurality of port buffers each coupled to said bus and to a corresponding one of said subsystems, each of said port buffers being adapted to establish a 2-stage bidirectional transfer link between its corresponding subsystem and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the subsystem protocol and the protocol of said node; and said controller including means for sequentially polling said port buffers; whereby said controller periodically sets the conditions for each port buffer to establish its transfer link.

Claim 14

A communication node for enabling a set of subsystems external to said node to communicate through the latter, each of said subsystems comprising a circuit including local data processing means for performing a specific control function relative to an operating unit responsive to said set of subsystems; said communication node comprising: a common node bus; a controller coupled to said bus; a plurality of port buffers each coupled to said bus and to a corresponding one of said subsystems, each of said port buffers being adapted to establish a 2-stage bidirectional transfer link between its corresponding subsystem and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the subsystem protocol and the protocol of said node; and said controller including means for sequentially polling said port buffers; whereby said controller periodically sets the conditions for each port buffer to establish its transfer link.

Claim 15

A communication node in accordance with claim 12 wherein one stage of each of said transfer links comprises means for providing bidirectional data transfers between the coupled subsystem and its corresponding port buffer timed by said subsystem; and wherein the second stage of each of said transfer links comprises means for providing bidirectional data transfers between said port buffer and said controller by way of said bus timed by said controller.

Claim 16

A communication node in accordance with claim 13 wherein said one stage of each of said transfer links is further adapted to perform data transfers from the coupled subsystem to its corresponding port buffer under port buffer control.

Claim 17

A communication node in accordance with claim 14 wherein said controller includes means for generating clock pulses; said means for providing data transfers in said second stage of each of said transfer links timed by said controller including means for transferring said information in clock pulse synchronism; and wherein data transfers in said one stage of each of said transfer links may be performed asynchronously with respect to said clock pulses.

Claim 18

A communication node in accordance with claim 14 wherein said intermediate data storage in each of said port buffers comprises a port buffer memory; each of said port buffers further comprising: first bidirectional switch means connected between said port buffer memory and the corresponding subsystem: second bidirectional switch means connected between said port buffer memory and said controller; and means for enabling said first and second switch means during mutually exclusive time intervals to stagger the data transfer operations in the respective stages of said transfer link.

Claim 19

A communication node in accordance with claim 16 wherein data and control information is organized into bytes, each data transfer between a subsystem and said controller being preceded by a pair of control bytes generated by said subsystem; each of said port buffers further comprising: latch means for temporarily storing said control bytes; and means operative in conjunction with each data transfer for directing said control bytes into said latch means and for directing said data bytes into said port buffer memory through one of said switch means.

Claim 20

A communication node in accordance with claim 17 wherein said control bytes define at least the direction of the data transfer and the number count of data bytes to be transferred; each of said port buffers further comprising: means responsive to said defined direction of data transfer to determine the order in which said first and second switch means are enabled; means operative during data transfers performed under port buffer control for counting the number of data bytes transferred; means for comparing the count of transferred data bytes with said number count entered by said control bytes; and means for terminating the transfer of data bytes when equality of the compared counts is reached.

Claim 21

A communication node in accordance with claim 18 wherein said control bytes further define a starting address; said controller comprising: means for generating clock pulses; a controller memory; said means timed by said controller including a controller address counter for sequentially addressing successive controller memory locations in clock pulse synchronism, said controller address counter being responsive to said control bytes to begin said sequential addressing at said starting address; and means responsive to said defined direction of data transfer to write said data bytes into, or to read said data bytes out from, said addressed controller memory locations.

Claim 22

A communication node in accordance with claim 14 or 19 wherein said control bytes are loaded into each port buffer by control signals generated by the corresponding subsystem; each of said port buffers comprising means responsive to said control signals and to said defined direction of data transfer to generate a transfer request; said sequential polling means comprising a port address counter for generating signals adapted to address successive port buffers of said node; means for initiating the requested data transfer if a transfer request generated by a port buffer is pending when said port buffer is addressed in sequence by said port address counter; and means for interrupting said sequential addressing of said port buffers for the duration of each data transfer; whereby contention between competing port buffers for access to said common node bus is effectively prevented by said controller.

Claim 23

A communication node in accordance with claim 20 wherein at least one peripheral station external to said node is adapted to communicate through said node; said node further comprising a port buffer coupled between said bus and said peripheral station; and each of said port buffers including means for decoding the count of said port address counter, said port buffers being substantially identical to each other except for said decoding means.

Claim 24

In a communication node: a common node bus; a controller coupled to said bus; a plurallity of port buffers each coupled to said bus and to an external circuit, each of said port buffers being adapted to establish a 2-stage bidirectional transfer link between its coupled external circuit and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the protocol of said external circuit and the protocol of said node; a first stage of each of said transfer links comprising means timed by said external circuit for providing bidirectional data transfers between said external circuit and its corresponding port buffer; the second stage of each of said transfer links comprising means timed by said controller for providing bidirectional data transfers between said controller and said port buffer; said controller comprising: means for sequentially polling said port buffers including a port address counter for generating a count adapted to address successive port buffers of said node; and means operative during each data transfer for holding said port address counter at the count of the addressed port buffer for the duration of said transfer; whereby said controller periodically sets the conditions for successive port buffers to establish a transfer link.

Claim 25

In a communication node: a common node bus; a controller coupled to said bus; a plurallity of port buffers each coupled to said bus and to an external circuit, each of said port buffers being adapted to establish a 2-stage bidirectional transfer link between its coupled external circuit and said controller wherein said port buffer is present in both stages to provide intermediate data storage and to translate between the protocol of said external circuit and the protocol of said node; a first stage of each of said transfer links comprising means timed by said external circuit for providing bidirectional data transfers between said external circuit and its corresponding port buffer; the second stage of each of said transfer links comprising means timed by said controller for providing bidirectional data transfers between said controller and said port buffer; said controller comprising: means for sequentially polling said port buffers including a port address counter for generating a count adapted to address successive port buffers of said node; and means operative during each data transfer for holding said port address counter at the count of the addressed port buffer for the duration of said transfer; whereby said controller periodically sets the conditions for successive port buffers to establish a transfer link.

Claim 26

Apparatus in accordance with claim 22 wherein said controller includes means for generating clock pulses; said means timed by said controller including means for carrying out said data transfers in said second stage in clock pulse synchronism; and means for carrying out said data transfers in said first stage asynchronously with respect to said clock pulses.

Claim 27

Apparatus in accordance with claim 23 wherein data and control information is organized into bytes, each data transfer through said transfer link being preceded by first and second control bytes provided by said external circuit and defining at least the direction of data transfer by means of a read/write bit and the number count of data bytes to be transferred; each of said port buffers further comprising: a port buffer memory adapted to provide said intermediate data storage; an information bus coupled to the corresponding external circuit and adapted to pass said control and data bytes therethrough; first and second latch means coupled to said information bus; means responsive to first and second control signals generated by said external circuit for loading said control bytes into said first and second latch means respectively; first switch means coupled between said port buffer memory and said information bus; second switch means coupled between said port buffer memory and said controller; a transfer byte counter coupled to said port buffer memory for addressing the latter and for counting data bytes transferred thereto; a comparator coupled to said first latch means and to said transfer byte counter, said comparator being adapted to generate a byte count equal signal when the count of data bytes actually transferred equals said number count; third latch means for generating a transfer request signal; means responsive when said transfer request signal is high for providing a transfer signal when the address of said port buffer is next generated in sequence by said port address counter; a ready circuit adapted to provide a ready signal indicative of the state of readiness of said transfer link to transfer data; means for setting said ready circuit when said byte count equal signal and said transfer signal are both high; said third latch means being adapted to provide said high transfer signal only when said ready signal is low; means for enabling said second switch means when said transfer signal is high; and means responsive to a third control signal generated by said external circuit for enabling said first switch means when said transfer signal is concurrently low; whereby said first and second switch means are enabled at mutually exclusive time intervals to stagger the transfer of data in said first and second stages.

Claim 28

Apparatus in accordance with claim 24 and further including means for terminating the transfer of data bytes, said last-recited means comprising: means for resetting said ready circuit when said second control signal, said ready signal and a read/write signal responsive to said read/write bit are concurrently high, or when said byte count equal signal is high while said transfer signal and said read/write signal are concurrently low; means for resetting said third latch means when said byte count equal signal and said tranfer signal are concurrently high; and means for resetting and for initializing said transfer byte counter when said byte count equal signal is high or when said second control signal and said ready signal are concurrently high.

Claim 29

Apparatus in accordance with claim 25, wherein said control bytes further define a starting address and wherein said controller further comprises: a controller memory; a controller address counter for sequentially addressing successive controller memory locations in clock pulse synchronism, said controller address counter being coupled to said first and second latch means and being responsive to the control byte information stored therein to begin said sequential addressing at said starting address; and means responsive when said transfer signal is high for writing data bytes into said addressed controller memory locations when said read/write signal concurrently assumes one of its two states, and for reading said data bytes out of said addressed memory locations when said read/write signal concurrently assumes the opposite state.